• Journal of Korean Academy of Oral and Maxillofacial Radiology
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• v.25 no.2
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• pp.363-373
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• 1995

The aim of this study was to evaluate and compare observer performance between conventional radiographs and their digitized images for the detection of bone loss in the bifurcation of mandiblar first molar. One dried human mandible with minimal periodontal bone loss around the first molar was selected and serially enlarged 17 step defects were prepared in the bifurcation area. The mandible was radiographed with exposure time of 0.12, 0.20, 0.25, 0.32, 0.40, 0.64 seconds, after each successive step in the preperation and all radiographs were digitized with IBM-PC/32 bit-Dx compatible, video camera (VM-S8200, Hitachi Co., Japan), and color monitor(Multisync 3D, NEC, Japan). Sylvia Image Capture Board for the ADC(analog to digital converter) was used. The obtained results were as follows: 1. In the conventional radiographs, the mean score of the readability was higher at the condition of exposure time with 0.32 second. Also, as the size of artificial lesion was increased, the readability of radiographs was elevated (P<0.05). 2. In the digital images, the mean score of the readability was higher at the condition of exposure time with 0.40 second. Also, as the size of artificial lesion was increased, the readability of digital images was elevated(P<0.05). 3. At the same exposure time, the mean scores of readibility were mostly higher in the digitized images. As the exposure time was increased, the digital images were superior to radiographs in readability. 4. As the size of lesion was changed, the digital images were superior to radiographs in detecting small lesion. 5. The coefficient of variation of mean score has no significant difference between digital images and radiographs.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.10
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• pp.139-146
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• 2002

We developed a motion capture system to utilize informations on the human walking motion. The system is composed of the mechanical and electronic devices to obtain the joint angle data and the software to analyze the obtained data and to transform the data into the input for a biped walking robot. The mechanical system is composed of a pair of links with 3 revolute joints, on which potentiometers are attached on joint axes to sense rotation angles. Analog signals from potentiometers are transformed into the digital data through the low pass filter and the A/D converter, and then which are stored at the computer. We analyzed the walking characteristics by applying FFT to the digital data, and then performed a 3-D computer simulation using the data. Finally, We apply the processed data to a biped walking robot.

• Tribology and Lubricants
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• v.11 no.5
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• pp.99-107
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• 1995

This paper reported research results to develop an algorithm of on-lin evaluation of surface profiles and roughness generated by turning. The developed module consisted of computer simulation of surface profiles using mechanism of cutting mark formation and cutting vibrations, and online measurement of cutting vibrations. The relative cutting vibrations between tool and worpkiece were measured through an inductance pickup at the rate of one sample per rotation of the workpiece. The sampling process was monitored using an encoder to avoid conceling out the phase lag between waves. The digital cutting signals from the Analog-to-Digital converter were transferred to the simulation module of surface profile where the surface profiles were generated. The developed algorithm or surface generation in a hard turning was analyzed through computer simulations to consider the stochastic and dynamic nature of cutting process. Cutting tests were performed using AISI 304 Stainless Steel and carbide inserts in practical range of cutting conditions. Experimental results showed good correlation between the surface profiles and roughness obtained using the developed algorithm and the surface texture measured using a surface profilemeter. The research provided the feasibility to monitor surface characteristics during tribelogical tests considering wear effect on surface texture in machining.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.18 no.8
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• pp.872-878
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• 2008

Many industrial operations require continuous or nearly-continuous operation of machines, interruption of which can result in significant cost loss. The condition monitoring of these machines has received considerable attentions in recent years. Rapid developments in semiconductor, computing, and communication with a remote site have led to a new generation of sensor called "smart" sensors which are capable of wireless communication with a remote site. The purpose of this research is to develop a new type of smart sensor for on-line condition monitoring. This system is addressed to detect conditions that may lead to equipment failure when it is running. Moreover it will reduce condition monitoring expense using low cost MEMS accelerometer. This system is capable for signal preprocessing task and analog to digital converter which is controlled by CPU. This sensor communicates with a remote site PC using TCP/IP protocols. The developed sensor executes performance tests for data acquisition accuracy estimations.

• ETRI Journal
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• v.32 no.2
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• pp.214-221
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• 2010

Radio frequency (RF) subsampling can be used by radio receivers to directly down-convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog-to-digital converter (ADC) as near the antenna as possible. Based on this, a band-pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second-order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second-order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second-order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.416-424
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• 2014

This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9A
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• pp.882-890
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• 2008

To overcome the limit of the time-domain based channel estimation caused by the ADC speed, this paper present a new BPM-UWB receiver where the channel estimations and the compensations are digitally performed in the frequency domain. We theoretically show that the channel estimation can be accomplished by exploiting the periodicity of a training sequence consisting of finite number of pulses. We also present the digital receiver structure to implement the proposed system and derive its BER performances. Through computer simulations, we show the proposed receiver can dramatically improve the BER performances due to the incorporation of the estimated channel frequency response.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.849-852
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• 2001

본 눈문에서는 뒤틀림, 응력, 압력[1], 토크, 가속도 등의 물리적인 동적 현상을 측정하여 수집된 데이터를 처리하기 위한 신호처리(Signal Processins) 기능이 결합되어 넓은 용도로 활용할 수 있는 센서 신호 수집 시스템을 구현하였다. 구현된 시스템은 data acquisition board 의 하드웨어와 소프트웨어로 나누어 볼 수 있다. 하드웨어의 구성은 아날로그부, 디지털부, 그리고 시스템 인터페이스 처리부로 되어 있다. 아날로그부에서는 센서신호를 받아서, PGA (Programmable Gain Amplifier)[2]와 Op-Amp를 사용하여 signal conditioning 처리하여 8차 Lowpass Filter 로 보낸다. Filtering 된 신호는 ADC (Analog to Digital Converter) 가 내장되어 있는 PIC(3) microcontroller로 보내져 AD변환과 디지털 신호 처리를 한다. 처리된 신호는 RS232 인터페이스를 통해 호스트 컴퓨터로 보내 사용자가 분석할 수 있도록 한다. 또한 LCD display 실시간으로 확인, 분석할 수 있으며 동시에analog output에서 센서신호의 특징을 분석 할 수 있도록 한다.