• Title/Summary/Keyword: Digital topology

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New Single-Phase Power Converter Topology for Frequency Changing of AC Voltage

  • Jou, Hurng-Liahng;Wu, Jinn-Chang;Wu, Kuen-Der;Huang, Ting-Feng;Wei, Szu-Hsiang
    • Journal of Power Electronics
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    • v.18 no.3
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    • pp.694-701
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    • 2018
  • This paper proposes a new single-phase power converter topology for changing the frequency of AC voltage. The proposed single-phase frequency converter (SFC) includes a T-type multi-level power converter (TMPC), a frequency decoupling transformer (FDT) and a digital signal processor (DSP). The TMPC can convert a 60 Hz AC voltage to a DC voltage and then convert the DC voltage to a 50 Hz AC voltage. Therefore, the output currents of the two T-type power switch arms have 50 Hz and 60 Hz components. The FDT is used to decouple the 50 Hz and 60 Hz components. The salient feature of the proposed SFC is that only one power electronic converter stage is used since the functions of the AC-DC and DC-AC power conversions are integrated into the TMPC. Therefore, the proposed SFC can simplify both the power circuit and the control circuit. In order to verify the functions of the proposed SFC, a hardware prototype is established. Experimental results verify that the performance of the proposed SFC is as expected.

A 256-Radix Crossbar Switch Using Mux-Matrix-Mux Folded-Clos Topology

  • Lee, Sung-Joon;Kim, Jaeha
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.6
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    • pp.760-767
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    • 2014
  • This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

Digital-controlled Single-phase Power-factor Correction Converter Operating in Critical Current Conduction Mode (임계전류도통모드로 동작하는 디지털제어 단상 역률개선 컨버터)

  • Jeong, Gang-Youl
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.7
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    • pp.2570-2578
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    • 2010
  • This paper presents a digital-controlled single-phase power-factor correction (PFC) converter operating in critical current conduction mode. The proposed converter utilizes the DC-DC boost converter topology for the PFC and operates the inductor current in critical conduction mode. Because the proposed converter is controlled digitally using a micom, its control circuit is simplified and the converter operates more effectively. This paper first explains the operational principles of the proposed converter and then analyzes the converter circuit. And this paper explains the implementation method of proposed converter with a detail design example, which is divided into software and circuit design parts. Also, it is shown through the experimental results of the prototype converter by the designed circuit parameters that the proposed converter has good performance as a single-phase PFC converter.

Accuracy Analysis of Topographic Survey Data for the Official Land Price Appraising (공시지가산정을 위한 지형·지세조사 자료의 정확도 분석)

  • Lee, Chang-Han;Sung, Chun-Ja
    • Journal of Cadastre & Land InformatiX
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    • v.48 no.1
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    • pp.153-167
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    • 2018
  • Despite many criticisms that topographic survey data for the official land price appraising collected annually using field survey method might be inaccurate, there is only few concrete research on it. This paper investigated whether the topographic survey data collected by a local government using field survey method is consistent with the data analyzed using the digital elevation model to examine its accuracy. The accuracy analysis indicated that 324 out of 1537 lots of land have inconsistent results which means the ratio of inconsistency is 17.36%. Among 11 areas studied, five had the inconsistency ratio above 20% while the worst one had 38.71%. The inconsistency ratio is generally higher for the rough terrain with irregular slope and high altitude while it is relatively lower for the terrain with smooth landform. The analysis results imply that there are limitations in investigating the topology by field survey method. Therefore, the official land price appraising policy should set precise criterion and change over to highly accurate geographic information analysis method to effectively and accurately examine topology, given the fact that the topology of the Republic of Korea has complicated features with irregular slope and altitude.

Development of Digital Watermarking Technology to Protect Cadastral Map Information

  • Kim, Jung-Yeop;Lee, Hyun-Joon;Hong, Sung-Eon
    • Journal of Korean Society for Geospatial Information Science
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    • v.18 no.3
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    • pp.57-65
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    • 2010
  • This research aimed to prevent illegal distribution and reproduction of digital cadastral map information using digital watermarking. To this end, a digital watermarking was developed in consideration of the properties of cadastral maps and based on watermarking methods, after which its performance was evaluated. A watermark key and a one-way function was used to compensate for the algorithm and, therefore, watermarking security, based on the existing research results. In these ways, the present method meets the requirements for fidelity, robustness, false positive rate and the maintenance of consistent topology. The advanced techniques suggested in this paper were devised so as to be suitable for vector data such as GIS and navigation data as well as cadastral maps. Moreover, if the existing methodology is further improved, it could be expected to be used even more widely.

A study on the transformation of cadastral map using Geo-Spatial Information System (지형공간정보체계를 활용한 지적도의 변환에 관한 연구)

  • Kim, Jung-Sik
    • Journal of Korean Society for Geospatial Information Science
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    • v.8 no.1 s.15
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    • pp.111-120
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    • 2000
  • A cadastral map that is base map on Land Information System is divided by two categories, graphical and digital cadastre. And digital cadastre can be displayed with location coordinates of nodes that depict parcel boundary on digital cadastral records. The transformation of digital cadastral records means that imported text data of node coordinate would be transformed into system data. This study was implemented to search reasons of errors resulted from transformation of graphic data and then to analyze the accuracy in terms of Position and area. For this, checking of software used in Geo-Spatial Information System was implemented at first and it was found that the accuracy is up by using double precision in coordinate transformation. On the position accuracy the errors at nodes was erased during making topology and the errors did not effect other nodes. On the area may the area errors because of being in error limit of allowable area had no problems in using of system.

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Digital Conversion of Analogue Cadastral Maps of Kathmandu Metropolitan City

  • Baral, Toya Nath;Acharya, Babu Ram;Subedi, Nab Raj
    • Proceedings of the KSRS Conference
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    • 2003.11a
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    • pp.973-977
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    • 2003
  • Land is the only immovable property that can be used, as a means for agricultural production as well as a means for mortgage for financing industrial or commercial enterprises. Spatial technologies play a key role in managing our land, water and natural resources. Cadastral data is a major component for the development of Land Information System. Therefore, systematic land registration system based on accurate and scientific cadastral map are found inevitable for poverty alleviation, good governance and women empowerment through security of their rights on property, as well as the planning and development of a sustainable environmental protection within Metropolitan city. Digital cadastral parcel is the fundamental spatial unit on which database is designed, created, maintained and operated. Availability of accurate and updated cadastral maps is a primary requisite for successful planning, policy formulating and maintenance of city utility services, which need cadastral and utility information together. Flawed cadastral maps can put land, revenue and taxation system at stake. Kathmandu the capital city of Nepal still is lacking utility maps combining cadastral information with the utility. There is an urgent need to have an effective, accurate and easy to access land revenue and utility services system within the urban areas which could be achieved after the production of reliable base maps and land registration system to guarantee land allocation and property rights which can well be achieved by digital conversion and correction of base cadastral maps. This paper highlights the drawbacks of the conventional cadastral maps and the possible advantages of digital cadastral maps over these. Also the problems, issues and implications during digital conversion and creating database of the same will be discussed.

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Simple Digital LCD Backlight Inverter using a Single-chip Microcontroller (단일칩 마이크로컨트롤러를 이용한 간단한 디지털 LCD 백라이트 인버터)

  • Jeong, Gang-Youl
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.2
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    • pp.461-468
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    • 2010
  • This paper presents a simple digital LCD backlight inverter using a single-chip microcontroller. The proposed inverter reduces the ignition voltage and eliminates the current spikes and hence improves the ignition behavior of the cold cathode fluorescent lamp(CCFL). Thus it increases the CCFL's life span. This is achieved by implementing a digital dimming control algorithm, that contains the soft-starting algorithm, all on a single-chip microcontroller. The inverter utilizes the full-bridge resonant circuit topology. The design example along with a simple analysis for the inverter is shown, and the experimental results of the designed prototype results in close agreement with the theoretical analysis and explanation. The overall system's power efficiency is approximately 85%. Compared with conventional inverters, the ignition voltage is reduced by around 30% without any lamp current spike occurring during the dimming control operation.

Novel LCD CCFL-backlight Electronic Ballast using the Phase-shift Full-bridge Inverter (위상천이 풀브리지 인버터를 이용한 새로운 LCD CCFL 백라이트 전자식 안정기)

  • Jeong, Gang-Youl
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.24 no.6
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    • pp.8-17
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    • 2010
  • This paper proposes a novel LCD CCFL-backlight electronic ballast using the phase-shift full-bridge inverter. The proposed electronic ballast reduces the ignition voltage and eliminates current spikes using the new digital dimming control applied with soft-starting. Thus the electronic ballast improves ignition behavior of the CCFL and hence increases the CCFL's life span. For this, this paper analyzes the full-bridge inverter topology of the proposed electronic ballast and explains the new digital dimming control algorithm applied to the ballast, briefly. And this paper shows a design example of the prototype circuit and explains an implementation method of the digital dimming control which is implemented on a single-chip microcontroller with software. This was implemented as actual prototype electronic ballast, and its experimental results showed that the proposed electronic ballast operates correctly. The ignition voltage of the prototype in the digital dimming operation was reduced about 30[%] compared with the conventional electronic ballast and there were not any current spikes.

A Digital Twin-based Approach for VANET Simulation in Real Urban Environments

  • Jonghyeon Choe;Youngboo Kim;Sangdae Kim
    • Journal of the Korea Society of Computer and Information
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    • v.29 no.8
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    • pp.113-122
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    • 2024
  • In this paper, we conducted a thorough investigation of existing simulators for running simulations of Vehicular Adhoc Networks (VANET) in realistic road environments, such as digital twins. After careful consideration, we chose a simulator that combines OSM (OpenStreetMap), SUMO (Simulation of Urban MObility), and OMNeT++ due to its open-source nature and efficient performance. Using this integrated simulator, we carried out VANET simulations in both simple virtual road environments and realistic road environments. Our findings revealed significant differences in VANET performance between the two types of environments, emphasizing the need to consider realistic road and traffic environments for reliable VANET operation. Furthermore, our simulations demonstrated significant performance variability, with performance degradation observed as vehicle density decreased and dynamic changes in network topology increased. These results underscore the importance of digital twin-based approaches in VANET research, highlighting the need to simulate real-world road and traffic conditions rather than relying on simple virtual road environments.