• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.2
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• pp.89-94
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• 2011

Today, the utilization of communication devices is being increased including information terminals, cell phones, handheld personal digital assistants (PDA) caused by the development of information and communication technology. The development of information and services is speeding up, whereas most communication devices have provided a inefficient hierarchical menu and sequential searching structure. In this study, the Adaptive User Interface is applied to the Bus Information Terminal(BIT) which is one of communication equipment installed in the bus stop. It will be based on analysis of unspecified individuals' preferences and user's directly personalization in the BIT prototype. We expect the results of this study to be possible to provide users with efficient and convenient information acquisition and contribute to the development of public transport use by improving the accessibility and usability of BIT.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.575-583
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• 2003

In thesis we applied the short or open reflection type for IQ vector modulator The open or short type is operated even exception of other redundancy circuit. Generally IQ vector modulator uses MESFET in performing reflection open or short, then minus voltage which is having complex structure is required to operate MESFET via IQ signal. However BJT can be substituted for MESFET, BJT is improved characteristics like as cutoff frequency, electron mobility and so on. We used BJT in IQ vector modulator which is compatible with TTL level in I,Q digital signal, and attached AGC function. We got the result of operations within ${\pm}$ 1$^{\circ}$ phase and ${\pm}$ 0.6 dB amplitude Variation With full range of 20 dB and Variation of ${\pm}$ 6$^{\circ}$ Phase and ${\pm}$ 0.5 dB amplitude Versus full temperature range.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• The KIPS Transactions:PartD
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• v.9D no.5
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• pp.827-836
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• 2002

Moving object management systems manage spatiotemporal data, which change their location over tine such as people, animals, and cars. These moving object management systems can be applied to vehicle location tracking, digital battlefield, location-based service, and so on. The existing moving object management systems only manage past or future location of the moving objects separately. Therefore, they cannot suggest estimation method of uncertain past or future location of the moving objects. In this paper, we propose a moving object management system, which not only manages historical data of the moving objects, but also predicts past and future location of the moving objects using historical data stored in database. We define the moving objects for vehicle location tracking and propose a moving object database structure. Finally, we suggest an execution model of the proposed system and apply the execution model to a virtual scenario for vehicle tracking.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.31 no.5
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• pp.411-419
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• 2013

Research on developing algorithms for building modeling such as extracting outlines of the buildings and segmenting patches of the roofs using aerial images or LiDAR data are active. However, utilizing information from the building model is not well implemented yet. This study aims to propose a scheme for search identical or similar shape of buildings by utilizing graph topology pattern matching under the assumptions: (1) Buildings were modeled beforehand using imagery or LiDAR data, or (2) 3D building data from digital maps are available. Side walls, segmented roofs and footprints were represented as nodes, and relationships among the nodes were defined using graph topology. Topology graph database was generated and pattern matching was performed with buildings of various shapes. The results show that efficiency of the proposed method in terms of reliability of matching and database structure. In addition, flexibility in the search was achieved by altering conditions for the pattern matching. Furthermore, topology graph representation could be used as scale and rotation invariant shape descriptor.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2465-2471
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• 2012

For the steel structures those are used in harsh sea environments, corrosion fatigue is a challenging issue in connection with design life. In this research, in order to investigate the influence of cathodic overprotection on the corrosion fatigue crack propagation behavior, corrosion fatigue crack propagation test under the condition of -950mV vs SCE was conducted by using of high tensile TMCP steel plate and the relationships between da/dN-${\Delta}K$ were obtained. At this test, when ${\Delta}K$ is low, the crack propagation rates were accelerated compared to those of seawater condition, however, when ${\Delta}K$ is high, the crack propagation rates were lower than those of seawater condition. As the cause for the acceleration and deceleration of corrosion fatigue crack propagation rates under the condition of cathodic overprotection, the role of hydrogen and calcareous deposits are discussed.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.1
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• pp.1-13
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• 2009

Flash memory is widely used as a storage medium of mobile devices such as MP3 players, cellular phones and digital cameras due to its tiny size, low power consumption and shock resistant characteristics. Currently, there are many studies to replace HDD with flash memory because of its numerous strong points. To use flash memory as a storage medium, FTL(Flash Translation Layer) is required since flash memory has erase-before-write constraints and sizes of read/write unit and erase unit are different from each other. Recently, new type of flash memory called "large block flash memory" is introduced. The large block flash memory has different physical structure and characteristics from previous flash memory. So existing FTLs are not efficiently operated on large block flash memory. In this paper, we propose an efficient FTL for large block flash memory based on FAST(Fully Associative Sector Translation) scheme and page-level mapping on data blocks.

• Korean Journal of Optics and Photonics
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• v.21 no.6
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• pp.235-240
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• 2010

We fabricate highly birefringent photonic crystal fiber with new structure using a stack and draw method. Fabricated fiber has two big air holes, one at each side of the outside air cladding region, leading to core ellipticity during the drawing process. Birefringence of the fabricated Hi-Bi PCF is measured to be $2.29{\times}10^{-4}$ (at 1550 nm).

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.51-55
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• 2007

This paper investigates the subthreshold behavior of Fin Field Effect Transistor (FinFET). The FinFET is considered to be an alternate MOSFET structure for the deep sub-micron regime, having excellent device characteristics. As the channel length decreases, the study of subthreshold behavior of the device becomes critically important for successful design and implementation of digital circuits. An accurate analysis of subthreshold behavior of FinFET was done by simulating the device in a 3D process and device simulator, Taurus. The subthreshold behavior of FinFET, was measured using a parameter called S-factor which was obtained from the $In(I_{DS})\;-\;V_{GS}$ characteristics. The value of S-factor of devices of various fin dimensions with channel length $L_g$ in the range of 20 nm - 50 nm and with the fin width $T_{fin}$ in the range of 10 nm - 40 nm was calculated. It was observed that for devices with longer channel lengths, the value of S-factor was close to the ideal value of 60 m V/dec. The S-factor increases exponentially for channel lengths, $L_g\;<\;1.5\;T_{fin}$. Further, for a constant $L_g$, the S factor was observed to increase with $T_{fin}$. An empirical relationship between S, $L_g$ and $T_{fin}$ was developed based on the simulation results, which could be used as a rule of thumb for determining the S-factor of devices.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.