• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.1-9
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• 2009

A full adders is an important component in applications of digital signal processors and microprocessors. Thus it is imperative to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional static CMOS and pass transistor logic. The carry-out generation circuit of the proposed full adder is different from the conventional XOR-XNOR structure. The output Cout of module III is generated from input A, B and Cin directly without passing through module I as in conventional structure. Thus output Cout is faster by reducing operation step. The proposed module III uses the static CMOS logic style, which results full-swing operation and good driving capability. The proposed 1bit full adder has the advantages over the conventional static CMOS, CPL, TGA, TFA, HPSC, 14T, and TSAC logic. The delay time is improved by 4.3% comparing to the best value known. PDP(power delay product) is improved by 9.8% comparing to the best value. Simulation has been carried out using a $0.18{\mu}m$ CMOS design rule for simulation purposes. The physical design has been verified using HSPICE.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.1
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• pp.24-36
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• 2003

The digital mobile communication will be developed till getting multimedia service in anyone, any where, any time. Theses requiring items are going to be come true via IMT-2000 system. Transmitting signal bandwidth of IMT-2000 system is 3 times as large as IS-95 system. That is mean peak to average of signal is higher than IS-95A system. So we have to design it carefully not to effect in adjacent channel. HPA(High Power Amplifier) located in the end point of system is operated in 1-㏈ compression point(Pl㏈), then it generates 3rd and 5th inter modulation signals. Theses signals affect at adjacent channel and RF signal is distorted by compressed signal which is operated near by Pl㏈ point. Then the most important design factor is how we make HPA having high linearity. Feedback, Pre-distorter and Feed-forward methods are presented to solve theses problems. Feed-forward of these methods is having excellent improving capacity, but composed with complex structure. Generally, Linearity and Efficiency in power amplifier operate in the contrary, then it is difficult for us to find optimal operating point. In this paper we applied algorithm which searches optimal point of linear characteristics, which is key in Power Amplifier, using minimum current point of error amplifier in 1st loop. And we made 2nd loop compose with new structure. We confirmed fabricated LPA is operated by having high linearity and minimum current condition with ACPR of -26 ㏈m max. @ 30㎑ BW in 3.515㎒ and ACLR of 48 ㏈c max@${\pm}$㎒ from 1W to 40W.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1075-1085
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• 2005

The purpose of this paper is to design the architecture for synchronization of MB-OFDM UWB system that is being processed the standardization for Alt-PHY of WPAN(Wireless Personal Area Network) at IEEE802.15.3a and to analyze the implementation loss due to 4 parallel synchronization architecture for design or link margin. First an overview of the MB-OFDM UWB system based on IEEE802.15.3a Alt-PHY standard is described. The effects of non-ideal transmission conditions of the MB-OFDM UWB system including carrier frequency offset and sampling clock offset are analyzed to design a full digital architecture for synchronization. The synchronization architecture using 4-parallel structure is then proposed to consider the VLSI implementation including algorithms for carrier frequency offset and sampling clock offset to minimize the effects of synchronization errors. The overall performance degradation due to the proposed synchronization architecture is simulated to be with maximum 3.08 dB of the ideal receiver in maximum carrier frequency offset and sampling clock offset tolerance fir MB-OFDM UWB system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.4
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• pp.49-59
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• 2017

Smart sensing plays a key role in a variety of IoT applications, and its importance is growing more and more together with the development of artificial intelligence. Therefore the importance of smart sensors cannot be overemphasized. However, most studies related to smart sensors have been focusing on specific application purposes, for example, security, energy saving, monitoring, and there are not much effort on researches on how to efficiently configure various types of smart sensors to be needed in the future. In this paper, a component-based framework with hierarchical structure for efficient construction of smart sensor is proposed and its application to smart home is designed and implemented. The proposed method shows that various types of smart sensors to be appeared in the near future can be configured through the design and development of necessary components within the proposed software framework. In addition, since it has a layered architecture, the configuration of the smart sensor can be expanded by inserting the internal or external layers. In particular, it is possible to independently design the internal and external modules when designing an IoT application service through connection with the external device layer. A small-scale smart home system is designed and implemented using the proposed method, and a home cloud operating as an external layer, is further designed to accommodate and manage multiple smart homes. By developing and thus adding the components of each layer, it will be possible to efficiently extend the range of applications such as smart cars, smart buildings, smart factories an so on.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1844-1866
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• 2011

In a home network system, each customer electronic device has the control data format chosen by its manufacturing company and there are various types of digital devices and protocols. Besides the mutual operating environments among the various devices are dissimilar. Affected by the characteristics explained above, home network systems can hardly support the crucial functions, such as data compatibility, concurrency control, and dynamic plug-in. Thus, the home network system shows relatively poor reusability. In this paper, we suggest design technique of configurable framework, which can widely support the variability, to increase the reusability of the home network system. We extract the different parts of the home network system as variation points, and define them as the variability types. We design a structure of configurable framework, and suggest customization technique of configurable framework through selection technique and plug-in technique. Also, we prove the reusability by applying the proposed framework and it methods to real-world home network systems and analyzing the measurement results of these case studies using software metrics. We can expect the proposed approach provides better reusability than the existing them by analyzing those measurement results.

• The Journal of the Convergence on Culture Technology
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• v.9 no.1
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• pp.111-118
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• 2023

The purpose of this study is to study jewelry designs presented to general consumers who seek new products and diversity. We would like to present a modular jewelry design with a structure and combination method that is distinct from jewelry in a multimodal replacement method that allows various product modules sold in the past to be worn interchangeably. Problems are likely to occur when a number of existing rather small parts are manufactured in a complex combination method, and difficulties may follow when consumers replace decorative parts and lose them in the process of assembling small fixture parts. Therefore, in order to reduce these problems, we try to make it different from jewelry products made with a simple and simple design so that it can be easily replaced and worn without the need for other coupling parts, and produced using the latest 3D printer (Rapid Prototyping). In this study, based on the experience and know-how gained while engaging in field work, it was possible to make a real object and focused on minimizing problems during the production process, and through this, time and economic loss can be reduced. The purpose of the study is to produce improved jewelry products by expressing more sophisticated and differentiated shapes by using 3D programs (CAD).

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.4
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• pp.11-17
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• 2020

This paper proposed the design of a new window signage system architecture, which utilized a window of a building, with attached LED for visible light communication. In this paper, the proposed method using the LED strip to transmit light data and receive the data through a HMD with a smart device camera. The LED strip attached to the existing building window, as a part of semi-transparent signage. Semi-transparent signage based on a controllable LED strip-modules and attached to the window used to provide entertainment contents and the information service to people through optical camera communication (OCC) as well. Also, this work suggests using the camera supplied Head Mounted Device (HMD) as an OCC receiver. The LED attached window signage system structure described in this paper can be utilized in various buildings infrastructure like house, shopping areas, industrial building, etc.