• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.90-96
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• 2014

This paper presents a practical linearization technique for a wide-band bang-bang digital phase locked-loop(BBDPLL) by selecting optimal loop gains. In this paper, limitation of the theoretical design method for BBDPLL is explained, and introduced how to implement practical BBDPLLs with CMOS process. In the proposed BBDPLL, the limited cycle noise is removed by reducing the proportional gain while increasing the integer array and dither gain. Comparing to the conventional BBDPLL, the proposed one shows a small area, low power, linear characteristic. Moreover, the proposed design technique can control a loop bandwidth of the BBDPLL. Performance of the proposed BBDPLL is verified using CppSim simulator.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.5
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• pp.71-78
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• 2012

This paper presents a digital control solution to process capacitor current feedback of high performance single-phase UPS for non-linear loads. In all UPS the goal is to maintain the desired output voltage waveform and RMS value over all unknown load conditions and transient response. The proposed UPS uses instantaneous load voltage and filter capacitor current feedback, which is based on the double regulation loop such as the outer voltage control loop and inner current control loop. The proposed DSP-based digital-controlled PWM inverter system has fast dynamic response and low total harmonic distortion (THD) for nonlinear load. The control system was implemented on a 32bit Floating-point DSP controller TMS320C32 and tested on a 5[KVA] IGBT based inverter switching at 11[Khz]. The validity of the proposed scheme is investigated through simulation and experimental results.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.04a
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• pp.230-233
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• 1987

A Dual Disital Phase Locked Loop is analyzeddesigned and tested. Two specific confisurations are considered generations second and thisrd order DPLL’s and it is found using a computer simulation and verified therretically . As a result of computer simulation the characteristcof designed I-Dullis better than the at of P-DPLL or C-Dull

• Architectural research
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• v.17 no.1
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• pp.21-30
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• 2015

This study examines the significance of digital fabrication of scaled physical models in the digital design process and highlights the integration of design computing and digital fabrication in architectural education. Advances in CAD/CAM technologies have increasingly influenced building design and construction practices by allowing the production of complex forms that were once difficult to design and construct using traditional technologies. At the advent of digital architecture, schools of architecture introduced digital technologies to their curriculum, focusing more on design computing than digital fabrication, preventing students from completely mastering digital technologies. The significance of digital fabrication for scaled physical models as a design media within the digital design loop is discussed. Two case studies of leading schools of architecture that are successful in building the bridge between both areas are given. These focus on the curricular structure to integrate both areas within design studios. Finally, a curricular structure offering students a balanced approach to these areas of knowledge is proposed based on what was learned from these case studies.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.240-243
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• 2001

This paper presents the digital controller using variable gain for single-phase power factor correction (PFC) converter. Generally, the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This is why input current is distorted under low input voltage. In particular, a digital controller has more time delay than an analog controller which degrades characteristics of control loop. So, it causes the problem that the gain of current control loop isn't increased enough. In addition, the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult. In this paper, the improved digital control method for single-phase power factor converter is presented. The variable gain according to input voltage and input current help to improve current shape. The 800W converter is manufactured to verify the proposed control method.

• Journal of IKEEE
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• v.27 no.3
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• pp.333-339
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• 2023

The global market for wearable devices is growing, driving demand for efficient PMICs. Wearable PMICs must be highly energy-efficient despite limited hardware resources. Advancements in process technology enable low-power consumption, but traditional analog LDO regulators face challenges with reduced power supply voltage. In this paper, a novel ADC design with a 3-bit continuous-time flash ADC for the coarse loop and a 5-bit discrete-time SAR ADC for the fine loop is proposed for digital LDO, achieving a 34.78 dB SNR and 5.39 bits ENOB in a 55-nm CMOS technology.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.9
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• pp.495-503
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• 2000

In this paper we propose a design procedure of loop-shaping two-degree-of-freedom H$\infty$ digital controller for sampled-data system. We extend the continuous time loop-shaping two-degree-of-freedom H$\infty$ control problem to sampled-data system. The configuration of generalized plant is modified for sampled-data system. And then using continuous lifting we obtain the digital controller. In the final stage of loop-shaping procedure the problem of absorbing weighting functions is discussed. We summarize this study to the design procedure and illustrate the application for an inverted pendulum on the cart.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1845-1851
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• 2016

In this paper, a design method for a wideband square loop antenna for Digital TV applications is studied. The proposed loop antenna is a square loop antenna combined with circular sectors to connect with central feed points. The square loop is used instead of the circular loop in order to miniaturize the antenna size. The input reflection coefficient and gain characteristics of the proposed antenna are analyzed to match with the 75 ohm port impedance for DTV applications. The effects of the gap between the circular sectors and the length of the square loop on the input reflection coefficient and gain characteristics are examined to obtain the optimal design parameters. The optimized antenna is fabricated on an FR4 substrate, and the experiment results show that it operates in the frequency band of 470-1,300 MHz for a VSWR < 2, which assures the operation in the DTV band.