• 디지털산업정보학회논문지
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• 제9권4호
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• pp.119-125
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• 2013

The amount of digital content grows exponentially by the development of the internet and the change of computing environments and the target also is getting wider. The industry using this digital content has been growing greatly. However, the distribution of pirated digital content is increasing using internet because digital content is easy to store and transmit and the damage is growing. In this paper, we propose safety trading system which can conceal the author's information safely in digital content in order to block illegal distribution of digital content. ARIA encryption algorithm is used to protect the concealed information of author in digital content and it is a help to track the illegal traders by doing fingerprinting of buyer information to digital content and managing the transaction information. The technical support for copyright dispute is to allow by providing the capability to verify illegal edit to original digital contents.

• 디지털콘텐츠학회 논문지
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• 제18권4호
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• pp.739-745
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• 2017

본 논문에서는 GPU 병렬 처리 하드웨어 아키텍처 내 최소 물리적 스레드 실행 단위(warp) 내에서 shifted sort 기반 k개 최근접 이웃 검색 기법을 구현하는 방법을 논의하고 일반적으로 동일한 목적으로 널리 사용되는 GPU 기반 kd-tree 및 CPU 기반 ANN 라이브러리와 비교한 결과를 제시한다. 또한 많은 애플리케이션에서 k가 비교적 작은 값이 필요한 경우가 많다는 사실을 고려해서 k가 warp 내부에서 직접 처리 가능한 2, 4, 8, 16개일 때 최적화에 집중한다. 구현 세부에서는 사용한 CUB 공개 라이브러리의 루프 내 메모리 관리 방법, GPU 하드웨어 직접 명령 적용 방법 등의 최적화 방법을 논의한다. 실험 결과, 제안하는 방법은 기존의 GPU 기반 유사 방법에 비해 데이터 지점과 질의 지점의 개수가 각각 $2^{23}$개 일 때 16배 이상의 빠른 처리 속도를 보였으며 이러한 경향은 처리해야 할 데이터의 크기가 커지면 더욱 더 커지는 것으로 판단된다.

• 전자공학회논문지C
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• 제35C권2호
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• pp.56-64
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• 1998

Multi-layered perceptrons that are a nonlinear neural network model, have been widely used for various applications mainly thanks to good function approximation capability for nonlinear fuctions. However, for digital hardware implementation of the multi-layere perceptrons, the quantization scheme using "look-up tables (LUTs)" is commonly employed to handle nonlinear signmoid activation functions in the neworks, and thus requires large amount of storage to prevent unacceptable quantization errors. This paper is concerned with a new effective methodology for digital hardware implementation of multi-layered perceptrons, and proposes a "piecewise affine approximation" method in which input domain is divided into (small number of) sub-intervals and nonlinear sigmoid function is linearly approximated within each sub-interval. Using the proposed method, we develop an expression and an error backpropagation type learning algorithm for a multi-layered perceptron, and compare the performance with the quantization method through Monte Carlo simulations on XOR problems. Simulation results show that, in terms of learning convergece, the proposed method with a small number of sub-intervals significantly outperforms the quantization method with a very large storage requirement. We expect from these results that the proposed method can be utilized in digital system implementation to significantly reduce the storage requirement, quantization error, and learning time of the quantization method.quantization method.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
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• pp.249-250
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• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• 디지털융복합연구
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• 제6권3호
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• pp.109-119
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• 2008

Although current RFID technology can provide wide advantages in food industry, most food companies do not consider widely adopting this technology yet. This paper presents analysis of how the effective implementation of RFID systems in food industry. To Measure the affecting factors, 19 items from Ketinger & Hackbarth, ABI Research, RFID Institutes and Researcher are selected. The validity and reliability of a questionnaire were examined through factor analysis and regression analysis was done by using the introduction of RFID systems and an achievement of ROI(Return On Investment) as dependent variables and the 4 factor scores from the factor analysis as independent variables. The results show that 2 factors are not only important in the introduction of RFID systems but also 3 factors also important for an achievements of ROI in particular.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1211-1214
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• 1998

Real-time implementation of Conjugate-Structure Algebraic CELP(CS-ACELP) is presented. ITU-T Study Group(SG) 15 has standardized the CS-ACELP speech coding algorithm as G.729. A real-time implementation of the CS-ACELP is achieved using 16 bit fixed point DSP16210 Digital Signal Processor (DSP) of Lucent Technologies. The speech coder has been implemented in the bit-exact manner using the fixed point CS-ACELP C source which is the part of the G.729 standard. To provide a multi-channel vocoder solution to digital communication system, we try to minimize the complexity(e.g., MIPS, ROM, RAM) of CS-ACELP. Our speech coder shows 15.5 MIPS in performance which enables 4 channel CS-ACELP to be processed with one DSP16210.

• 디지털산업정보학회논문지
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• 제8권1호
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• pp.41-46
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• 2012

In this paper, An efficient circuit design algorithm considering constraint is proposed. The proposed algorithm sets up in time constraint and area constraint, power consumption constraint for a circuit implementation. First, scheduling process for time constraint. Select the FU(Function Unit) which is satisfied with time constraint among the high level synthesis results. Analyze area and power consumption of selected FUs. Constraint set for area and power constraint. Device selection to see to setting condition. Optimization circuit implementation in selected device. The proposed algorithm compared with [7] and [8] algorithm. Therefore the proposed algorithm is proved an efficient algorithm for optimization circuit implementation.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권9호
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• pp.657-662
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• 2004

The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.

• 디지털융복합연구
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• 제7권1호
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• pp.99-109
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• 2009

Recently, many enterprises are interest in implementing Radio Frequency IDentification (RFID). However, they have some difficulty in implementing RFID because of incompleteness of RFID technology and uncertainty of Return on Investment (ROI). Even though usefulness of RFID are recognized, many enterprises are just interested in planning of RFID rather than implementation of RFID. Among successful factors of RFID implementation, Information Technology (IT) capability is the most important one. If enterprises have systematic IT capability, it would make positive attitude to implement RFID. In addition, it will provide trust about RFID and promote adoption of RFID implementation. This study, therefore, empirically analyzed the relationships of trust, attitude, IT capability, and intention to RFID adoption using Partial Least Squares (PLS) approach. The result show useful guidelines and practical implication in implementing RFID.

• Journal of Electrical Engineering and Technology
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• 제3권2호
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• pp.243-253
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• 2008

This paper deals with the analysis, design, and implementation of a single phase AC-DC Zeta converter with high frequency transformer isolation and power factor correction(PFC) in two modes of operation, discontinuous current mode of operation(DCM), and continuous current mode of operation(CCM). A Digital Signal Processor(DSP) based implementation is carried out for validation of the Zeta converter developed design in discontinuous mode of operation. A comparison of both modes of operation is presented for a 1kW power rating from the point of view of steady state and dynamic behavior, power quality, simplicity, control technique, device rating, and converter size. The experimental results of a developed prototype of Zeta converter are presented for validation of the developed design. It is observed that CCM is most suitable for higher power applications where it requires some complex control and sensing of the additional variables.