• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.91-94
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• 2000

This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

• Journal of Broadcast Engineering
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• v.9 no.4 s.25
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• pp.357-370
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• 2004

In this paper we propose Digital Signal Processing (DSP) techniques for the Equalization Digital On-Channel Repeater(EDOCR) in the ATSC digital TV (DTV) System. DSP techniques consist of demodulation. baseband equalization, and remodulation. Since the time delay caused by signal processing in the EDOCR can seriously affect the performance of ATSC legacy receivers, it is required that the processing time should be minimized as much as possible. To achieve this goal, we focus on the reduction of the EDOCR's time delay with the minimization of its performance degradation. In addition, we present recommended proper parameters for hardware implementation based on extensive simulation result.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.174-178
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• 2001

An improved stationary frame-based digital current control technique for a permanent magnet (PM) synchronous motor is presented. Generally, the stationary frame current controller is known to provide the advantage of a simple implementation. However, there are some unavoidable limitations such as a steady-state error and a phase delay in the steady-state. On the other hand, in the synchronous frame current regulator, the regulated currents are dc quantities and a zero steady-state error can be obtained through the integral control. However, the need to transform the signals between the stationary and synchronous frames makes the implementation of a synchronous frame regulator complex. Although the PI controller in the stationary frame gives a steady-state error and a phase delay, the control performance can be greatly improved by employing the exact decoupling control inputs for the back EMF, resulting in an ideal steady-state control characteristics irrespective of an operating condition as in the synchronous PI decoupling controller. However, its steady-state response may be degraded due to the inexact cancellation inputs under the parameter variations. To improve the control performance in the stationary frame, the disturbance is estimated using the time delay control. The proposed scheme is implemented on a PM synchronous motor using DSP TMS320C31 and the effectiveness is verified through the comparative simulations and experiments.

• Journal of Communications and Networks
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• v.15 no.5
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• pp.496-503
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• 2013

In an orthogonal frequency division multiplexing system, conventional interpolation techniques cannot correctly balance performance and overhead when estimating dynamic long-delay channels in single frequency networks (SFNs). In this study, classical filter analysis and design methods are employed to derive a complex interpolator for maximizing the resistible echo delay in a channel estimator on the basis of the correlation between frequency domain interpolating and time domain windowing. The coefficient computation of the complex interpolator requires a key parameter, i.e., channel length, which is obtained in the frequency domain with a tentative estimation scheme having low implementation complexity. The proposed complex adaptive interpolator is verified in a simulated digital video broadcasting for terrestrial/handheld receiver. The simulation results indicate that the designed channel estimator can not only handle SFN echoes with more than $200{\mu}s$ delay but also achieve a bit-error rate performance close to the optimum minimum mean square error method, which significantly outperforms conventional channel estimation methods, while preserving a low implementation cost in a short-delay channel.

• Journal of Power Electronics
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• v.1 no.2
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• pp.88-98
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• 2001

An improved stationary frame-based digital current control technique for a permanent magnet(PM) synchronous motor is presented. Generally, the stationary frame current controller is known to provide the advantage of a simple implementation. However, there are some unavoidable limitations such as a steady-state error and a phase delay in the steady-state. On the other hand, in the synchronous frame current regulator the regulated currents are dc quantities and a zero steady-state error can be obtained through the integral control. However, the need to transform the signals between the stationary and synchronous frames makes the implementation of a synchronous frame regulator complex. Although the PI controller in the stationary frame gives a steady-state error and a phase delay, the control performance can be greatly improved by employing the exact decoupling control inputs for the back EMF., resulting in an ideal steady-state control characteristics irrespective of an operating condition as in the synchronous PI decoupling controller. However, its steady-state response may be degraded due to the inexact cancellation inputs under the parameter variations. To improve the control performance in the stationary frame, the disturbance is estimated using the time delay control. The proposed scheme is implemented on a PM synchronous motor using DSP TMS320C31 and the effectiveness is verified through the comparative simulations and experiments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.724-730
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• 2002

Digital communication systems are required to cause the minimum interference to adjacent channels, they must therefore employ the linear power amplifiers. In respect to linear power amplifiers, there are many linearization techniques. Feedforward power amplifier represent very wide bandwidth and high linearization capability. In the feedforward systems, overall efficiency is reduced due to the loss of delay line. In this paper, delay filter instead of transmission delay line adapted to get more high efficiency. Experimental results showed that ACLR (Adjacent Channel Leakage Ratio) has improved 17.43(dB), which is added 3.44(dB) by using the delay filter.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.3
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• pp.45-53
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• 2019

Moving image sharing technology has developed various servers and programs for personal broadcasting. In this paper, we propose the method of transmitting the multiple moving image, including the output channel of external streaming server. It also implements and tests multiple real-time broadcast channel automatic transmission systems that assign multiple output channels to automatic output channels. As a result of the experiment, it is easy to allocate moving image to broadcast channels that are output through the external streaming server's output channels regardless of the size of the streaming server, enabling the management of efficient output channels at the time of transmission of multiple moving image. The moving image can be provided through streaming method regardless of the type of moving image from the moving image provider terminal, and the moving image transmission can be controlled in various ways, including adding and changing channels for which the moving image is sent, and sending delayed to the moving image.

• Journal of the Korea Institute of Military Science and Technology
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• v.24 no.1
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• pp.31-40
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• 2021

The multi-channel video streaming system is an essential device for future ground combat vehicles. For the system, the application of digital interfaces is required instead of the direct analog method to support selectable multiple channels. However, due to the characteristics of the digital interfaces that require en/decoding and signal conversion, the system should support the ability to adapt to quality and delay requirements depending on how video data is utilized. To support addressed issue, this study designs and emulates the multi-channel compressed-video streaming system of ground combat vehicle's fire control system based on commercial standards. Using the system, this study analyzes the quality of video according to the rotational speed of the acquisition device and Glass-to-Glass (G2G) delay between video acquisition and display devices according to video compression rates. Through these experiments and analysis, this paper presents the design direction of the system having scalability on the latest technology while providing high-quality video data streaming flexibly.

• ETRI Journal
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• v.26 no.6
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• pp.545-554
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• 2004

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.346-351
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• 1998

In design of a digital current controller for a 3-phase (3 ) voltage-source (VS) PWM converter, its conventional model, i.e., stationary or synchronous reference frame model, is used in obtaining its discretized version. It introduces, however, inherent errors since the following practical problems are not taken into consideration: the characteristics of the space vector-based pulse-width modulation (SVPWM) and the time delays in the process of sampling and computation. In this paper, the new hybrid reference frame model of the 3 VS PWM converter is proposed considering these problems. In addition, the direct digital current controller based on this model is designed without any prediction or extrapolation algorithm to compensate the time delay. So the control algorithm is made very simple. It represents no steady-state error in input current control and has the optimized transient responses. The validity of the proposed algorithm is proved by the computer simulation and experimental results.