• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.18-27
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• 2004

In this paper, we presents an analytical simulation procedure for evaluation in baseband digital modulated signals distortions in the present of RF power amplifier(SSPA) nonlinear behavior and backoff operations of OFDM wireless transmission system. we obtained the optimum nonlinear transfer function of designed SSPA with the SiGe HBT bias currents of OFDM multi-channel wireless transmission system and compared this transfer function to SSPA nonlinear modeling functions mathematically, we finds optimum bias conditions of designed SSPA. With the derived nonlinear modeling function of SSPA, We analysed the PSD characteristics of in-band and out-band output powers of SSPA EVM measurement results of distorted constellation signals with the input power levels of SSPA. The results of paper can be applied to find the SSPA linearly with optimum bias currents and determine the SSPA input backoff bias for AGC control circuits of SSPA.

• Annals of Clinical Neurophysiology
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• v.2 no.1
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• pp.8-12
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• 2000

Purpose : The rapid development and wide popularity of Digital EEG(DEEG) is due to its convenience, accuracy and applicability for quantitative analysis. These advantages of DEEG make one hesitate to use analog EEG(AEEG). To assess the advantage of DEEG system utilizing AEEG(DAEEG) over conventional AEEG and the clinical applicability, a DAEEG system was developed and applied to animal model Methods : Sprague-Dawley rat as status epilepticus model were used for collecting the EEG data. After four epidural electrodes were inserted and connected to 8-channel analog EEG(Nihon-Kohden, Japan), continous. EEG monitoring via computer screen was done from two rats simultaneously. EEG signals through analog amplifier and filters were digitized at digital signal processor and stored in Windows-based pentium personal computer. Digital data were sampled at a rate of 200 Hz and 12 bit of resolution. Acquisition software was able to carry out 'real-time view, sensitivity control and event marking' during continuous EEG monitoring. Digital data were stored on hard disk and hacked-up on CD-ROM for off-line review. Review system consisted of off-line review, saving and printing out interesting segment and annotation function. Results: This DAEEG system could utilize most major functions of DEEG sufficiently while making a use of an AEEG. It was easy to monitor continuously compared to Conventional AEEG and to control sensitivity during ictal period. Marking the event such as a clinical seizure or drug injection was less favorable than AEEG due to slowed processing speed of digital processor and central processing unit. Reviewing EEG data was convenient, but paging speed was slow. Storage and management of data was handy and economical. Conclusion : Relatively simple digital EEG system utilizing AEEG can be set-up at n laboratory level. It may be possible to make an application for clinical purposes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.52-57
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• 2011

This paper presents a 4-channel optical transmitter circuit realized in a $0.18{\mu}m$ CMOS technology for high-speed digital interface. Particularly, the VCSEL driver exploits the feed-forward technique, and the pre-amplifier employs the pulse-width control. Thus, the optical transmitter operates at the bias current up to 4mA and the modulation current from $2{\sim}8mA_{pp}$. with the pulse-width distortion compensated effectively. The 4-channel optical transmitter array chip occupies the area of $1.0{\times}1.7mm^2$ and dissipates 35mW per channel at maximum current operations from a single 1.8V supply.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.51 no.2
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• pp.178-186
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• 2018

A chirp-echo data acquisition and processing system was developed for use as a simplified, PC-based chirp echo-sounder with some data processing software modules. The design of the software and hardware system was implemented via a field-programmable gate array (FPGA). Digital signal processing algorithms for driving a single-channel chirp transmitter and dual-channel receivers with independent TVG (time varied gain) amplifier modules were incorporated into the FPGA for better real-time performance. The chirp-echo data acquisition and processing system consisted of a notebook PC, an FPGA board, and chirp sonar transmitter and receiver modules, which were constructed using three chirp transducers operating over a frequency range of 35-210 kHz. The functionality of this PC-based chirp echo-sounder was tested in various field experiments. The results of these experiments showed that the developed PC-based chirp echo-sounder could be used in the acquisition, processing and analysis of broadband acoustic echoes related to fish species identification.

• ETRI Journal
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• v.30 no.5
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• pp.729-734
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• 2008

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling-time constraints. This makes the use of traditional closed-loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast-settling response. The AGC has been implemented in a 0.35 ${\mu}m$ standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 ${\mu}s$.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1013_1014
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• 2009

In this paper, the electrical interfaces used in between COMS satellite bus and Ka-band communication payload are analyzed to verify the robustness of data bus. The purpose of the serial data bus of satellite is to allow serial data transfer between one bus controller or source equipment to several user terminals or slave equipments. A serial data bus in COMS satellite is mainly used for Channel Amplifier and Digital Control Unit of Ka-band Payload.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.16-20
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• 2002

This paper describes the resistive FET mixer with low IF for the 4-Ch DBF(Digital Beam Forming) receiver with LNA(Low Noise Amplifier). This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 2.09 ㎓, 2.08 ㎓ and 10㎒, respectively. The RF input power, LO input power and Vgs are used -10㏈m, 6㏈m and -0.4 V, respectively. In the 4-Ch resistive FET mixer with LNA, the measured IF and harmonic components of 10㎒, 20㎒, 2.09㎓ and 4.17㎓ are about -12.5 ㏈m, -57㏈m, -40㏈m and -54㏈m, respectively. The IF output power observed at each channel of 10㎒ is about -12.5㏈m and it is higher 27.5 ㏈m than the maximum harmonic component of 2.09㎓. Each IF output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.3
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• pp.115-122
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• 2015

Global Positioning System (GPS) is used in various fields such as communications systems, transportation systems, e-commerce, power plant systems, and up to various military weapons systems recently. However, GPS receiver is vulnerable to jamming signals as the GPS signals come from the satellites located at approximately 20,000 km above the earth. For this reason, various anti-jamming techniques have been developed for military application systems especially and it is also required for commercial application systems nowadays. In this paper, we proposed a dual-channel Global Navigation Satellite System (GNSS) RF ASIC for digital pre-correlation anti-jam technique. It not only covers all GNSS frequency bands, but is integrated low-gain/attenuation mode in low-noise amplifier (LNA) without influencing in/out matching and 14-bit analogdigital converter (ADC) to have a high dynamic range. With the aid of digital processing, jamming to signal ratio is improved to 77 dB from 42 dB with proposed receiver. RF ASIC for anti-jam is fabricated on a 0.18-μm complementary metal-oxide semiconductor (CMOS) technology and consumes 1.16 W with 2.1 V (low-dropout; LDO) power supply. And the performance is evaluated by a kind of test hardware using the designed RF ASIC.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.505-508
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• 2000

본 논문에서는 16채널 혹은 8채널의 센서를 통해 들어오는 저주파대역의 아날로그 신호를 수집하고. 수집된 데이터를 실시간으로 처리하기 위한 고속의 신호처리 기능이 결합된 통합 DSP (Digital Signal Processor)시스템을 구현하였다. 구현된 시스템은 휴대가 용이하도록 소형으로 설계되어 있으며 노트북 등의 이동형 장비에 활용되도록 USB 인터페이스를 채택하였으며, 장치간의 네트워크 구성이 가능하도록 Ethernet 인터페이스를 추가하였다 Digital Signal Processor는 Texas Instrument 사의 TMS320C6701 부동소수점 연산방식의 고성능 DSP를 사용하여 16채널의 실시간 신호 분석이 가능하게 하였으며, ICP 센서 구동용 전류 공급부를 내장하여 센서 선택의 폭을 넓히었고, programmable gain amplifier인 PGA202증폭기를 사용하여 입력신호가 작을 경우 최대 1000배, 즉 60dB까지 입력신호를 증폭하여 수집 및 분석할 수 있다. 200kSPS의 샘플링 레이트와 16bit resolution을 가지는 AD976 A/D converter를 사용하여 채널당 0～6kHz의 신호대역폭을 가지며,differential 입력시 8 채널,single ended 입력시 16 채널의 입력 신호의 수집 및 분석이 가능하다. Windows 응용프로그램에서는 사용자가 원하는 입력신호 및 스펙트럼 실시간 분석, 입력신호 기록 및 저장, RPM 측정 및 분석, 외부 트리거 및 레벨 트리거를 이용한 입력신호 제어와 수집된 데이터를 바탕으로 원하는 제어가 가능한 응용프로그램 제작에 활용될 라이브러리가 포함된다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.