• Title/Summary/Keyword: Digital audio processor

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Design on MPEC2 AAC Decoder

  • NOH, Jin Soo;Kang, Dongshik;RHEE, Kang Hyeon
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1567-1570
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    • 2002
  • This paper deals with FPGA(Field Programmable Gate Array) implementation of the AAC(Advanced Audio Coding) decoder. On modern computer culture, according to the high quality data is required in multimedia systems area such as CD, DAT(Digital Audio Tape) and modem. So, the technology of data compression far data transmission is necessity now. MPEG(Moving Picture Experts Group) would be a standard of those technology. MPEG-2 AAC is the availableness and ITU-R advanced coding scheme far high quality audio coding. This MPEG-2 AAC audio standard allows ITU-R 'indistinguishable' quality according to at data rates of 320 Kbit/sec for five full-bandwidth channel audio signals. The compression ratio is around a factor of 1.4 better compared to MPEG Layer-III, it gets the same quality at 70% of the titrate. In this paper, for a real time processing MPEG2 AAC decoding, it is implemented on FPGA chip. The architecture designed is composed of general DSP(Digital Signal Processor). And the Processor designed is coded using VHDL language. The verification is operated with the simulator of C language programmed and ECAD tool.

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Effects Analysis of DRAM for Digital Signal Processor Performance (디지털 신호처리 프로세서의 성능에 대한 DRAM의 영향 분석)

  • Lee, Jongbok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.18 no.3
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    • pp.177-183
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    • 2018
  • Currently, digital signal processing systems are used extensively in image processing, audio processing, filtering, and equalizations, etc. In addition, the importance of DRAM, which has a great influence on the performance of an digital signal processor has been increased, making research on DRAM actively conducted in industry and academia. Therefore, it is important to have a more accurate DRAM model in order to obtain reliable results when evaluating the performance of a digital signal processor through simulation. In this paper, we developed a digital signal processor simulator capable of inter-working with a DRAM simulator. With the simulator, we analyzed the influence of the DRAM model which operates correctly on a cycle-by-cycle basis, on the performance of the digital signal processor by using the UTDSP digital signal benchmark.

Implementation of the Audio CODEC for Digital Audio Broadcasting Service (디지털 오디오 방송 서비스를 위한 오디오 코덱의 구현)

  • 장대영;홍진우
    • Journal of Broadcast Engineering
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    • v.6 no.1
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    • pp.66-71
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    • 2001
  • This paper Introduces an implementation of MPEG-2 AAC codec system for digital audio broadcasting. This system consists of the encoder and the decoder. This system includes MPEG-2 system multiplexing and demultiplexing modules for Interfacing to the ETRI-DAB system. Four DSPs are adopted for the encoder and three DSPs for 7he decoder. Each DSP Processes system control. 1/0 control, audio signal processing. multiplexing and demultiplexing. This Paper also discusses some near future estimations relaxed to the DAB system and it\`s services. Currently a stereo audio codec is available but multi-channel audio codec and MPEG-4 audio cosec wall be also Implemented.

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A Low Power Multi-Function Digital Audio SoC

  • Lim, Chae-Duck;Lee, Kyo-Sik
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.399-402
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    • 2004
  • This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

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Implementation of the AAC Audio CODEC for Digital Audio Broadcasting (디지털 오디오 방송을 위한 AAC 오디오 코덱 구현)

  • 장대영;홍진우
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2000.11b
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    • pp.43-48
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    • 2000
  • This paper introduces MPEG-2 AAC codec system fur digital audio broadcasting. This system consists of encoder and decoder, and this system provides MPEG-2 system multiplexing and demultiplexing functions. Four DSPs are adopted fur encoder and three DSPs fur decoder. Each DSP processes system control, I/O control, and audio signal processing, multiplexing and demultiplexing. This paper also discusses about some near future estimations related to DAB system and services. And at the end of this paper describes about future development plans.

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A Design on the Vector-Processor of 2048 Point MDCT/IMDCT for Digital Audio (디지털 오디오를 위한 2048포인트 MDCT/IMDCT 벡터프로세서 설계)

  • Gu, Dae Seong;Jeong, Yang Gwon;Kim, Jong Bin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.9C
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    • pp.851-859
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    • 2003
  • 최근 사용자들의 멀티채널 선호도는 급속도로 전파되고 있다. MPEG은 동영상 및 음향시스템의 데이터 압축기술을 제공하는데, 현재 각광을 받고있는 것이 디지털 오디오이다. MPEG 표준안은 MPEG-1오디오 알고리즘을 MPEG-2 알고리즘에 동일하게 사용해도 멀티채널 및 5.1채널 사운드륵 제공한다. MDCT(Modified Discrete Cosine Transform)는 TDAC(Time Domain Aliasing Cancellation)에 기반을 두고있는 변형이산 여현 변환을 나타낸 것이다. 본 논문에서는 오디오 부분의 핵심이라 할 수 있는 MDCT/IMDCT(Inverse MDCT) 알고리즘을 최적화하여 효율적인 알고리즘을 제안하였다. 그리고 연산과정에서 중복되는 영역을 묶음으로써 연산에 필요한 계수를 줄였다. 최적화 전에 비해 코사인 계수를 0.5%이하로 최적화하였고, 승산에서 0.098%, 가산에서 0.58% 효율을 보였다. 알고리즘 검증은 C언어를 사용하여 검증하였고, 최적화된 알고리즘을 적용하여 마이크로 프로그램 방식의 하드웨어 구조론 설계하였다.

An Implementation of Highly Integrated Signal Processing IC for HDTV

  • Hahm Cheul-Hee;Park Kon-Kyu;Kim Hyoung-Gil;Jung Choon-Sik;Lee Sang-keun;Jang Jae-Young;Park Sung-Uk;Chon Byung-Hoan;Chun Kang-Wook;Jo Jae-Moon;Song Dong-il
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2003.11a
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    • pp.69-72
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    • 2003
  • This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

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A study on the implementation of a digital video/audio system to support multi-audio format (다양한 오디오 포맷을 지원하는 비디오/오디오 시스템 구현에 관한 연구)

  • Park In-Gyu
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.43 no.4 s.310
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    • pp.123-132
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    • 2006
  • In this paper, the digital video and audio system is improved so that various digital video data formats in DVD disc, and digital audio data formats through the S/PDIF ports may be decoded. It is not easy to implement all decoding functions of video and audio by a DVD processor. The special structure in audio decoding circuit is proposed in this system so as to have simultaneously almost same video and audio performance in quality. By dividing the decoding circuit separately into video and audio part, the audio quality can be dramatically improved together with supporting several audio formats and with several effects. In order to satisfy the perfect audio system to support to audio decoding formats, it is just enough to get the expensive, complicated decoder. However, it may be not easy to get this expensive decoder in near future. Therefore it is rather to adopt the downloading method by which the host should download the appropriate code into memory by detecting the corresponding audio bit streams. It is proved that this method may be efficient in the point of sharing resource of audio data for video decoding.

A Compensation of Linear Distortion for Loudspeaker Using the Adaptive Digital Filter (적응 디지탈 필터를 이용한 확성용 스피커의 선형 왜곡 보상)

  • 전희영;차일환
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 1995.06a
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    • pp.165-170
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    • 1995
  • In this paper, it is attempted to apply the adaptive digital signal processing to compensate for a linear distortion of a loudspeaker and implement a real time hardware for that purpose. The real time system is implemented by using the DSP56001, a general purpose signal processor, as a host processor and the DSP56200, a cascadable adaptive FIR filter peripheral chip, as an adaptive digital filter. The system has 1000 taps at a 44.1kHz. After inverse modeling of under_compensation_speaker, the system reduces loudspeaker's linear distortions by pre-processing an input audio signal to loudspeaker. The experiment shows satisfactory results; after adaption with white noise as input signal for 60sec, the flat amplitude and linear phase frequency characteristics is found to lie over a wide frequency range of 100Hz to 20kHz.

A study on digital sound reception systems for ships (선박용 디지털 음향수신장치 연구)

  • Kim, Hyungjong;Kim, Jeongchang
    • Journal of Advanced Marine Engineering and Technology
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    • v.38 no.9
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    • pp.1125-1130
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    • 2014
  • In this paper, we propose a sound reception system against surrounding noise for ships based on digital signal processing technologies. In order to suppress unwanted surrounding noises, a digital band-pass filter is designed, which the pass-band of the filter is between 70Hz to 820Hz. Also, we develope a sound direction indicating algorithm with 4 microphones. After filtering the audio signals from 4 microphones, the developed sound direction indicating algorithm can indicate 8 directions. In addition, we implement prototype board for the sound reception using a digital signal processor chip and audio codecs, and verify the proposed algorithm.