• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.378-386
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• 2017

A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-nm CMOS technology. Measured results show that the worst SFDR performances are 60 dBc and 55 dBc in the 1st and 2nd Nyquist bands, respectively, when operating at 650 MHz clock frequency. The total power consumption is 64 mW, and the active area occupies $0.25mm^2$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 심포지엄 논문집 정보 및 제어부문
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• pp.252-254
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• 2006

The recent improvement in the performance of digital processor, the application of control technology, which used in the HVDC(High Voltage Direct Current) system with the digital processors, has increased. Having this research development as the basis, this paper presents an achievement of progression by tuning the parameter of PI controller based on Genetic Algorithms(GAs) and by controlling with PI controller with a developed simulator by applying the Matrix operating function, voltage source switching element, modified nodal analysis which can include transformer and the backward Euler which does not create the problem of numerical oscillation. As a result, I expect this development in the simulator HVDC System to bring more application in the field of control technology research with an expanded practicality.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.461-463
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• 2018

본 논문에서는 동기식 광 네트워크 SDH(Synchronous Digital Hierarchy)망의 장거리 무선 전송을 위해 필요한 연동 장치를 연구하였다. SDH 방식의 기본 전송단위인 STM-1 신호와 155Mbps급 Synchronous Etherenet의 무선 전송 구현 및 측정 방법을 제안한다. STM-1 전송과 Synchronous Ethernet 전송을 위해 클럭 동기 회복 기능을 제공하며, 안정적인 동기 확보를 위해 예비 클럭 전환 기능을 설계 하였다.

• 공학기술논문지
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• 제5권4호
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• pp.349-353
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• 2012

Recently, Mobile multimedia equipments as smart phone and tablet pc requirement is increasing and this market is also being expanded. These mobile equipments require large multi-media function, so more power consumption is required. For these reasons, the needs of power management IC as switching type dc-dc converter and linear regulator have increased. DC-DC buck converter become more important in power management IC because the operating voltage of VLSI system is very low comparing to lithium-ion battery voltage. There are many people to be concerned about digital DC-DC converter without using external passive device recently. Digital controlled DC-DC converter is essential in mobile application to various external circumstance. This paper proposes the DC-DC Buck Converter using the AVR RISC 8-bit micro-processor control. The designed converter receives the input DC 18-30 [V] and the output voltage of DC-DC Converter changes by the feedback circuit using the A/D conversion function. Duty ratio is adjusted to maintain a constant output voltage 12 [V]. Proposed converter using the micro-processor control was compared to a typical boost converter. As a result, the current loss in the proposed converter was reduced about 10.7%. Input voltage and output voltage can be displayed on the LCD display to see the status of the operation.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2006년도 하계학술대회
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• pp.57-61
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• 2006

As high speed internet users are tremendously increasing, three are keenly in need of development of high speed portable internet technology which can provide high quality wireless internet service cheaply even in the mobile. Unlike the FDD-CDMA, TDD-OFDMA has relatively poor wave environment with inducing interference, fading and delay because it agrees to multi-carrier modulation method and time-division radio telecommunication system. To solve this problem, it is necessary to develop repeater operating by digital signal processing method which have more strict wireless channel control and wave signal processing technology over TDD telecommunication equipments. This thesis is dealing with design and implementation of Digital RF Repeater which implemented 'Synchronization Acquisition Unit', 'TDD signal switching Unit', 'Feedback Signal Cancellation Unit'. Over this argument, we will develop digital RF repeater with more cheap, more adaptive in wave environment like oscillation control, adaptive wave monitoring and output increasing and having control function as a result it will be helpful for success in high speed portable internet service business.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1028-1031
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• 2003

The implementation of PI controller with the FPGA is for controlling the speed of DC motor in the digital system. FPGA is assigned to 1. Outer speed control loop. The signal from the speed comparison will be in the PI controlling form transfer function of Direct Form I or PI Parallel Form. 2.Inner current control loop. The signal from the current comparison will be converted into switching function in sliding mode condition. Its output will be a controller of DC motor in the next step. The result from using FPGA will be close to the value of simulation in the analog control system. The sampling rate 40 kHz and 16 bit of 2's complement data are defined in this presentation.

• 한국통신학회논문지
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• 제23권6호
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• pp.1562-1574
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• 1998

본 논문에서는 ATM(Asynchronous Transfer Mode) 교환기 시스템에 T1, E1 및 부분적으로 E1급 속도의 중 저속 HDSL(High-rate digital subscriber line) 정합 기능을 개발하고, 근단누화(NEXT), 임펄스. 선로 잡음(power line noise) 및 접지 임피던스(longitudinal) 잡음 같은 주요 전송 손실이 존재하는 0.4 mm 및 0.5 mm의 기존 전화가입자 선로(UTP, Unshielded twisted pair)를 사용하는 CSA(Carrier serving areas) 선로 모델을 이용하여 $10^{-7}$의 BER(Bit error rates)의 전송 성능을 만족하기 위한 가입자 서비스 전송 거리 성능을 평가하였다. HDSL은 DSI, ISDN 기본 속도 접속 및 DLC 피더에 사용될 것이며 광 케이블과 인터페이스될 것이다. 또한, HDSL 시잔 전망을 제시한다.

• 한국광학회지
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• 제8권6호
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• pp.492-499
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• 1997

굽은 비선형 도파로를 이용한 완전 광 스위치와 굽은 비선형 Y 분기각을 갖는 도파로를 이용한 완전 광 논리 연산소자를 제안하였다. 제안된 완전 광 스위치와 완전 광 논리 연산소자는 굽은 비선형 도파로를 따라가는 비선형파의 전파에 기초를 두고 있다. 빔의 전파특성은 도파로의 비선형성과 입력 파워, 도파로의 굽은 각도 등의 파라미터에 의해 좌우되므로 파라미터를 변화시켜 가면서 파워의 출력 특성을 계산해 보았다. 또한, 비선형 물질로 빠져 나오는 파워를 다양한 위치의 검출기에서 계산함으로써 특정한 검출기의 위치에서 가장 이상적인 디지털 스위칭 특성을 찾았고 도파로 끝과 비선형 물질로 빠져 나오는 파워의 비율에 의해 다양한 논리 함수(AND, OR, XOR)를 구현해 보았다.

• 디지털융복합연구
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• 제10권11호
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• pp.351-358
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• 2012

본 연구는 강유역의 홍수 및 수질 오염을 보다 효율적으로 관리하기 위해 고품질의 영상정보를 고속으로 전달할 수 있는 광통신 장치로 기존의 장치에 비해 저렴하면서도 네트워크 광선로 및 장비상태를 실시간으로 모니터링이 가능한 시스템을 제안한다. 홍수 통제용으로 이용되는 통신장비는 주로 무인함체 내에 설치되어 있고 이는 장거리 구간의 강 하구에 위치한 홍수 통제소에서 운용하고 있기 때문에 광 케이블의 절단이나 노화 등에 의한 통신 장해 발생시 신속한 대처가 어려운 문제가 있다. 따라서, 본 연구에서는 광 선로를 이용하여 고품질의 영상정보를 고속으로 전달할 수 있으면서도 위와 같은 사고 발생시 1차적으로 이중화 광 케이블 보호절체 기능을 이용하여 문제를 해결하고, 실시간 모니터링 기능으로 발생 지점을 실시간으로 통보해줌으로써 보다 효율적인 관리가 가능한 시스템을 제안하였다. 또한, 제안된 시스템은 지능형 교통 시스템 등 다양한 분야에서 폭넓게 활용이 가능할 것으로 판단된다.

• Journal of Power Electronics
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• 제15권1호
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• pp.190-201
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• 2015

This paper uses the switching function approach to present a simple state model of the Vienna-type rectifier. The approach introduces the relationship between the DC-link neutral point voltage and the AC side phase currents. A novel direct power control (DPC) strategy, which is based on the sliding mode control (SMC) for Vienna I rectifiers, is developed using the proposed power model in the stationary ${\alpha}-{\beta}$ reference frames. The SMC-based DPC methodology directly regulates instantaneous active and reactive powers without transforming to a synchronous rotating coordinate reference frame or a tracking phase angle of grid voltage. Moreover, the required rectifier control voltages are directly calculated by utilizing the non-linear SMC scheme. Theoretically, active and reactive power flows are controlled without ripple or cross coupling. Furthermore, the fixed-switching frequency is obtained by employing the simplified space vector modulation (SVM). SVM solves the complicated designing problem of the AC harmonic filter. The simplified SVM is based on the simplification of the space vector diagram of a three-level converter into that of a two-level converter. The dwelling time calculation and switching sequence selection are easily implemented like those in the conventional two-level rectifier. Replacing the current control loops with power control loops simplifies the system design and enhances the transient performance. The simulation models in MATLAB/Simulink and the digital signal processor-controlled 1.5 kW Vienna-type rectifier are used to verify the fast responses and robustness of the proposed control scheme.