• Bulletin of the Korean Space Science Society
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• 2003.10a
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• pp.107-107
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• 2003

GPS Receiver는 위성에 위치 정보와 시간 정보등을 제공하고 navigation을 관리하며 이에 관련된 signal을 processing하는 역할을 한다. 2005년에 발사 예정인 KOMPSAT-2 위성에는 Alcatel에서 제작된 Topstar 3000이 사용된다. Topstar 3000은 RF 부분과 digital 처리부분으로 구성된 GPS core부분과 MLD-STD_1553, DC-DC converter, 그리고 Ovened-controlled Oscillator(OCXO)부분으로 구성되는 option module 부분으로 구성되어 있다. 본 논문에서는 GPS Signal Simulator로 KOMPSAT-2의 실제 궤도를 구현해서 Sun-Point Mode와 Earth-Point Mode 등 여러가지 Mode 에서 GPS Receiver의 시간, 위치, 속도 정보의 정확성에 대한 성능이 분석된다.

• Journal of Power System Engineering
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• v.14 no.1
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• pp.5-10
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• 2010

Both the accuracy and stability of the clock get from the GPS receiver are considered in the range of pps. And we verified the system clock stability of a micro-controller system using the pps pulse supplied by the GPS receiver. In complex system of digital processing, the rack of precise timing signal may cause the serious problem or breakdown accident. To get rid of these undesirable problems, we introduced VCXO circuit to a micro-controller system to preserve high accurate clock stability.

• Transactions on Electrical and Electronic Materials
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• v.10 no.6
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• pp.222-226
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• 2009

The objective of this study is to share multimedia contents included in existing digital devices and to solve the problems of an increase in installation fees and non-environmentally friendly interiors. This study designed a new digital signal transmitter and receiver using power line transmission and HDMI in order to solve the problems in the existing systems. The transmitter and receiver designed in this study used an AD9867BCPZ PLC chip in which the transmission came from digital signals originating in a PC, and the system architecture was configured so that the outputs signals were connected to a TV from the receiver. The experiment was implemented by adding a Video Test Generator, a USBPre external sound card, and Smaart Live 6 for analyzing the characteristics of the configured system. In the video test results, it was verified that communication was actively implemented, and the image quality showed a constant level from the measurement of the captured video. In the case of the sound, it was verified that more than 90% of the sound signals were normally transmitted and received from the examination of their phases and magnitudes. Thus, the performance of the system designed in this study was verified, which leads to the resolution of some of the problems found in current digital devices.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1666-1668
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• 2004

By wireless transmission data, there is high possibility to get distortion and lose by noise and barrier on wireless. If the data check damaged and lost at receiver, can't make it clear and can't judge whether this data is right or not. Therefore, by wireless transmission data need the data error check algorithm in order to decrease the data's distortion and lose and to monitoring the transmission data as real time. This study consists of RF station for wireless transmission, Water Level Meter station for water level measurement and Error check algorithm for error check of transmission data. This study is also that investigation and search for error check algorithm in order to wireless digital data transmission in condition of the least data's damage and lose. Designed transmitter and receiver with one - chip micro process to protect to swell the volume of circuit. Had designed RF transmitter - receiver station simply by means of ATMEL one - chip micro process in the systems. Used 10mW of the best RF power and 448MHz-449MHz on frequency band which can get permission to use by Frequency Law made by Korean government

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.796-800
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• 2004

The main research on this paper is to model on-chip inductor in digital CMOS technology by using the foundry parameters and the physical structure. The s-parameters of a spiral inductor are extracted from the modeled equivalent circuit and then compared to the results obtained from HFSS. The structure and material of the inductor used for modeling in this work is identical with those of the inductor fabricated by CMOS process. To show why the modeled inductor instead of ideal inductor should be used to design a RF system, we designed dual band RF front-end receiver and then compared the results between when using the ideal inductor and using the modeled inductor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9C
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• pp.905-913
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• 2006

In the impulse radio ultra-wideband communication systems, the residual timing offset exists when the acquisition and tracking of the timing synchronization is well done. And the offset affects the performance of the system dramatically. In order to compensate the offset, we present the digital phase-locked loop that uses the reference signal in the correlation detection receiver. First, we show the degradation of BER performance that is caused by the offset, and then compensation process of the timing tracker and performance improvement. In this paper, the timing detector in the tracker operates at the sampling period of frame level uses the correlation between received and reference signal. Also, we present the performance comparison by using the computer simulation results for different Gaussian monocycle pulses.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2005.11a
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• pp.117-120
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• 2005

A Digital Broadcasting Satellite (DBS) receiver converts digital A/V streams received from a satellite to analog NTSC A,/V signals in real-time. Multi-tasking is an efficient way to improve the utilization of the processor core in real-time applications. In this paper, we propose a hybrid approach with a balanced trade-off between hardware kernel and multi-tasking programming to increase a system throughput. First, the schedulability of the critical hard real-time tass in the DBS receiver is verified by using a simple feasibility test. Then. several soft real-time tasks are thoughtfully programmed to satisfy functional requirements of the system.

• Journal of the Korea Institute of Military Science and Technology
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• v.22 no.2
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• pp.249-254
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• 2019

A Digital Transmitter/Receiver Module(DTRM), which is an essential part in active phased-array radar systems, generates a high heat density, and needs to be properly cooled for stable operation. A tile-type DTRM that is a stacking structure of multi-layer components was modeled with simplification and heat dissipation characteristics of the DTRM model were studied using computational fluid dynamics(CFD) simulations. Most of the heat was dissipated by the heat conduction through the cold plate, but the heat transfer by the forced convection on top of the DTRM also was found to play an important role in the thermal management. Under the given conjugated heat transfer environment, the DTRM was confirmed to secure a stable operating temperature range.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.3
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• pp.115-122
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• 2015

Global Positioning System (GPS) is used in various fields such as communications systems, transportation systems, e-commerce, power plant systems, and up to various military weapons systems recently. However, GPS receiver is vulnerable to jamming signals as the GPS signals come from the satellites located at approximately 20,000 km above the earth. For this reason, various anti-jamming techniques have been developed for military application systems especially and it is also required for commercial application systems nowadays. In this paper, we proposed a dual-channel Global Navigation Satellite System (GNSS) RF ASIC for digital pre-correlation anti-jam technique. It not only covers all GNSS frequency bands, but is integrated low-gain/attenuation mode in low-noise amplifier (LNA) without influencing in/out matching and 14-bit analogdigital converter (ADC) to have a high dynamic range. With the aid of digital processing, jamming to signal ratio is improved to 77 dB from 42 dB with proposed receiver. RF ASIC for anti-jam is fabricated on a 0.18-μm complementary metal-oxide semiconductor (CMOS) technology and consumes 1.16 W with 2.1 V (low-dropout; LDO) power supply. And the performance is evaluated by a kind of test hardware using the designed RF ASIC.