• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.308-310
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• 2008

향후 가까운 미래에 정부에서 주도하고 있는 10만호 보급사업 등을 포함한 대규모 태양광발전산업의 보급에 따라 특정지역에서는 계통연계형 태양광 전력변환기(PV PCS)의 고밀도 연계가 예상된다. 이 때 지금까지는 이론적으로만 가능할 것으로 여겨졌던 현상 인 단독운전 현상이 발생할 수 있는 확률이 높아지게 된다. 본 논문에서는 전력변동기법 중 하나인 무효전력변동기법에 대하여 단독운전검출 성능을 향상시키기 위한 한 방법으로 Digital Phase-Locked-Loop(DPLL)의 주파수계산을 이용하여 그 효용성을 PSIM 시뮬레이션을 통하여 검증하였다.

• 전자공학회논문지A
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• 제33A권3호
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• pp.47-54
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• 1996

In this paper we propose a new timing recovery method by means of utilizing service data filling rate instead of timing information of transmitter. A proposed algorithm controls the phase locked loop in the opposite direction ot data filling rate of FIFO in receiver, and it is based on the fact that average of cell jitters is zero. The proposed method is simple compared with timing information method of transmitter. It can be utilized for timing recovery in synchronous digital hierarchy as well as in plesiochronous digial hierarchy without common reference clocks in end-to-end erminals. We implement the interactive video communication system and test the proposed algorithm. As a result, we hav econfirmed that it yields good perfomrnces in terms of jitters characteristics and hardware complexity.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.963-964
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• 2006

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.200-202
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• 2005

In this paper, improved rotor position estimation for position sensorless control system of the SRM (Switched Reluctance Motor) is presented. For more accurate rotor position estimation, the PLL (Phase Locked Loop) based position interpolation is adapted. In the current-flux-rotor position lookup table based rotor position estimation, the inherent current and flux-linkage ripple can cause the position estimation error. Instead of the conventional low-pass filter, the PLL based position interpolation technique is used for the better dynamic performance. The developed rotor position estimation scheme is realized using TMS320F2812 digital signal processor and prototype 1-hp SRM.

• ETRI Journal
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• 제29권4호
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• 전력전자학회논문지
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• 제20권2호
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• pp.182-192
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• 2015

This study develops a digital control scheme with power factor correction for a front-end converter in an electric vehicle battery charger. The front-end converter acts as the boost-type switching-mode rectifier. The converter assumes the two roles of the battery charger, which include power factor control and robust charging performance. The proposed control scheme consists of a charging control algorithm and a grid current control algorithm. The scheme aims to obtain unity input power factor and robust performance. Based on the linear average model of the converter, a constant-current constant-voltage charging control algorithm that passes through only one proportional-integral controller and a current feed-forward path is proposed. In the current control algorithm, we utilized a second band pass filter, a single-phase phase-locked loop technique, and a duty-ratio feed-forward term to control the grid current to be in phase with the grid voltage and achieve pure sinusoidal waveform. Simulations and experiments were conducted to verify the effectiveness of the proposed control scheme, both simulations and experiments.

• 한국전자파학회논문지
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• 제25권11호
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• pp.1190-1196
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• 2014

본 논문은 넓은 고도 범위와 낮은 측정 오차를 갖는 주파수 변조 연속파(FMCW) 레이더 고도계의 설계 방안을 제안한다. 측정 고도의 동적 범위를 줄이기 위해 전파 고도계의 송신 경로에 광 지연선을 적용하여 넓은 고도 범위를 얻을 수 있다. 송신 전력과 수신단 이득을 제어하여 또한 수신 전력의 동적 범위를 줄일 수 있다. 더불어, 직접 디지털 합성기를 사용하여 변조 선형성을 향상시키고, 기준 클럭 신호를 위상 고정 루프의 옵셋(offset) 주파수로 사용하여 위상잡음을 최소화함으로써 낮은 고도 측정오차를 갖는다.

• Journal of Power Electronics
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• 제18권6호
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• pp.1830-1843
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• 2018

In this paper, the generation of a reference current and voltage signal based on a Kalman filter is offered for a 3-phase 4wire UPQC (Unified Power Quality Conditioner). The performance of the UPQC is improved with source voltages that are distorted due to harmonic components. Despite harmonic and frequency variations, the Kalman filter is capable enough to determine the amplitude and the phase angle of load currents and source voltages. The calculation of the first state is sufficient to identify the fundamental components of the current, voltage and angle. Therefore, the Kalman state estimator is fast and simple. A Kalman based control strategy is proposed and implemented for a UPQC in a distribution system. The performance of the proposed control strategy is assessed for all possible source conditions with varying nonlinear and linear loads. The functioning of the proposed control algorithm with a UPQC is scrutinized and validated through simulations employing MATLAB/Simulink software. Using a FPGA SPATRAN 3A DSP board, the proposed algorithm is developed and implemented. A small-scale laboratory prototype is built to verify the simulation results. The stated control scheme for the UPQC reduces the following issues, voltage sags, voltage swells, harmonic distortions (voltage and current), unbalanced supply voltage and unbalanced power factor under dynamic and steady-state operating conditions.

• 한국인터넷방송통신학회논문지
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• 제12권5호
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• pp.1-9
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• 2012

본 논문은 레이더 시스템에 적용되는 고성능 PLL 주파수 합성기를 설계하고, 그 성능을 분석하였다. 소형화제작을 위해 PLL 간접합성방식을 적용하였으며, 광대역특성에서 우수한 위상잡음과 고속의 주파수합성시간을 갖기 위해 offset 방식의 PLL에 DDS를 기준신호로 설계 하였다. 또한, offset PLL에서 고속의 주파수 변환을 위해 DAC를 이용하여 coarse tune을 적용하였다. 이러한 구조에서의 성능 예측을 위해 각각의 잡음원에 대해 모델링을 적용하여 출력위상잡음을 예측하였으며, 제작결과와 비교 분석하였다. 그 결과 simulation과 측정결과가 일치함을 확인하였으며, 100KHz 옵셋 주파수에서 -126dBc/Hz의 우수한 위상잡음 특성과 10usec 이내의 고속의 주파수변환시간을 갖는 항공기용 레이더 주파수합성기를 설계하였다.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2006년도 International Symposium on GPS/GNSS Vol.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.