• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1325-1332
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• 2009

In this paper, we design a 2.4 GHz bio-radar system that can detect human heartbeat and respiration signals with small size and improved noise performance using single circular-polarized antenna and phase-locked loop. The demonstrated bio-radar system consists of single circular-polarized antenna with $90^{\circ}$ hybrid, low-noise amplifier, power amplifier, voltage-controlled oscillator with phase-locked loop circuits, quadrature demodulator and analog circuits. To realize compact size, the printed annular ring stacked microstrip antenna is integrated on the transceiver circuits, so its dimension is just $40\times40mm^2$. Also, to improve signal-to-noise-ratio performance by phase noise due to transmitter leakage signal, the phase-locked loop circuit is used. The measured results show that the heart rate and respiration accuracy was found to be very high for the distance of 50 cm without the additional digital signal processing.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.8
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• pp.623-628
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• 2013

The retrodirective array antenna system is operated faster than existing techniques of beamforming due to its less complexity. Therefore, it is effective for beam tracking in the environment of fast vehicle. On the other hand, it also has difficulty in estimating AOA according to multipath environment or multiuser signals. To improve the certainty of estimating AOA), this article proposes hybrid digital retrodirective array antenna systme combined with MUSIC algorithm. In this paper, the digital retrodirective array antenna system is designed according to the number of antenna array by using only one digital PLL which finds angle of delayed phase. And we evaluate the performance of the digital retrodirective array antenna for the high speed tracking application. Performance is studied by simulink when the speed of mobile is 300km/h and the distance between transmitter and receiver is 100m and then we have to confirm the performance of the system in multi path environment. As a result, the mean of AOA (Angle Of Arrival) error is $4.2^{\circ}$ when SNR is 10dB and it is $1.3^{\circ}$ when SNR is 20dB. Consequently, the digital RDA shows very good performance for high speed tracking due to the simple calculation and realization.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.950-953
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• 1987

A wave difference method(WDH) phase detector for timing recovery is designed in the digital subscriber loop receiver. This paper describes the architecture and experimental results of the WDM, tankless timing extraction PLL. The results show that the designed WDM timing extraction circuit have stable jitter performance without the use of high precision LC tank circuit.

• Journal of information and communication convergence engineering
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• v.6 no.1
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• pp.47-50
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• 2008

A novel high channel efficiency transceiver based on a fast acquisition frequency synthesizer has been designed. The direct digital synthesis (DDS) technique is applied and a simple memory look-up table is incorporated to expedite channel acquisition. The technique simplifies the frequency control process in the transceiver and thus reduces the channel switching time. As a result, the channel efficiency is improved. The designed transceiver is ideal for frequency hopping mobile communication applications.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.271-274
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• 1999

This paper proposes a simple architecture of digital dividing block in dual-modulus prescaler phase-locked loop used in the wireless communication. Proposed architecture eliminates a swallow counter in the conventional one and demonstrates the advantages in reducing the power consumption and the gate-counts. Therefore, it is suitable for small die area and low power applications. The circuit is designed in a standard 0.35${\mu}{\textrm}{m}$ CMOS process.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.336-339
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• 1999

In this paper, we describe the accommodation of the PRML technique for the high speed and high density optical disk systems, which has been very effective in the high density HDD systems. To make the PRML technique adequate for the optical disk systems, the channel modeling and the simulation are performed. Finally, the architecture has been designed and realized into an ASIC. We have focused on the differences of PRML architecture between the HDD system and the optical disk system, and the digital realization of the PLL which has been realized with analog circuits.

• The Journal of the Acoustical Society of Korea
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• v.5 no.2
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• pp.13-18
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• 1986

디지틀 데이터 전송시 수신기에서 또는 중계기에서 송신 데이터를 구하기 위해서는 타이밍 클럭 을 복원해야 한다. 대개의 실장된 경우에서는 PLL을 이용하는데, 이때 시스템/랜덤 지터가 발생되고 또 중계기가 늘어남에 따라서 생성된 지터가 누적되는데 이것을 해석하였다. 90 Mbps 광통신 시스템에 적 용하여 테이블 1,2,3,4와 같은 결과를 얻었으며, 시스템 지터가 랜덤 지터보다 더 급격히 누적됨을 알았 고, 또한 댐핑팩터가 커짐에 따라 지터 누적이 양화됨을 알았다.

• Proceedings of the KIEE Conference
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• 1997.07a
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• pp.146-148
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• 1997

This paper investigates the position sensorless control of switched reluctance motor. The system consists of the position detection circuit by the new phase detection algorithm, digital logic commutator, PLL for speed control and 4-phase inverter. The performances in the proposed system are verified through the experiment.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.270-274
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• 2002

본 논문은 고속 무선랜에 적용하고 있는 OFDM시스템에서 국부발진기의 위상잡음에 의해서 기저대역의 채널에서 나타나는 위상변위특성을 해석하고, 국부발진기를 포함하는 PLL시스템에서 위상잡음 변화를 수치적인 해석을 하였다. OFDM신호를 QPSK, 16QAM 변조신호로 전송하였을 경우, 위상잡음에 따른 관계를 변조신호의 성상도 및 BER관계로써 분석하였다.