• 디지털산업정보학회논문지
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• 제12권2호
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• pp.7-14
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• 2016

In this paper presents a low power algorithm using a feasible cluster generation method considered glitch. The proposed algorithm is a method for reducing power consumption of a given circuit. The algorithm consists of a feasible cluster generation process and glitches removal process. So that glitches are not generated for the node to which the switching operation occurs most frequently in order to reduce the power consumption is a method for generating a feasible cluster. A feasible cluster generation process consisted of a node value set, dividing the node, the node aligned with the feasible cluster generation. A feasible cluster generation procedure is produced from the highest number of nodes in the output. When exceeding the number of OR-terms of the inputs of the selected node CLB prevents the signal path is varied by the evenly divided. If there are nodes with the same number of outputs selected by the first highest number of nodes in the input produces a feasible cluster. Glitch removal process removes glitches through the path balancing in the same manner as [5]. Experimental results were compared with the proposed algorithm [5]. Number of blocks has been increased by 5%, the power consumption was reduced by 3%.

• 디지털콘텐츠학회 논문지
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• 제12권3호
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• pp.347-353
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• 2011

HIPERLAN/2에서 무선채널은 중앙제어방식으로 운영되는 액세스 포인트에 의해서 할당되며, MAC 프로토콜은 TDMA/TDD를 기반으로 한다. 상향링크로 데이터 전송이 필요한 이동단말은 RCH 채널을 통하여 액세스 포인트에게 무선자원을 요청한다. 각 MAC 프레임마다 RCH 수를 변경하는 중요한데, RCH 수가 많이 할당되면 무선자원의 낭비를 초래하며, RCH 수가 적게 할당되면 이동단말간의 충돌이 증가하고 액세스 포인트에 접속하는 시간도 길어진다. 따라서 RCH 수는 트래픽에 따라 적절하게 할당되어야 한다. 이러한 관점에서 본 논문에서는 이전 MAC 프레임에서 메시지 전송에 성공한 회수와 실패한 회수를 기반으로 RCH 수를 동적으로 할당하는 방안을 제안하였다. 제안한 방안의 효율성을 입증하기 위해 시뮬레이션을 수행하여 분석하였다.

• 한국의학물리학회지:의학물리
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• 제32권2호
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• pp.50-58
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• 2021

Purpose: In this study, we investigated the relationship between the noise characteristics and the number of projected images in tomosynthesis using a digital phantom. Methods: The digital phantom consisted of a columnar phantom in the center of the image and a spherical phantom with a diameter of 80 pixels. A virtual scan was performed, and 128 projected images (Tomo_w/o) of the phantoms were obtained. The image noise according to the Poisson distribution was added to the projected images (Tomo_×1). Furthermore, another projected image with additional noise was prepared (Tomo_×1/2). For each dataset, we created datasets with 64 (half) and 32 (quarter) projections by removing the even-numbered images twice from the 128 (fully) projected images. Tomosynthesis images were reconstructed by filtered back projection (FBP). The modulation transfer function (MTF) was estimated using the sphere method, and the noise power spectrum (NPS) was estimated using the two-dimensional Fourier transform method. Results: The MTFs did not change between datasets, and the NPSs improved as the number of projected images increased. The noise characteristics of the Tomo_×1_half images were the same as those of the Tomo_×1/2_full. Conclusions: To achieve a reduction in the patient dose in tomosynthesis acquisition, we recommend reducing the number of projected images rather than reducing the dose per projection.

• 대한전자공학회논문지
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• 제16권3호
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• pp.19-27
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• 1979

디지탈 필타를 마이크로프로세서를 이용하여 설계하였다. 포커스 수를 사용하여 수를 표시하므로서 승제산을 고속화하였고, 가감산은 환산표를 활용하여 처리하였다. 이리하여 삼차의 저역통과 디지탈 필타의 샘플이 500 (samples/sec)까지 처리 되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1185-1187
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• 1987

Digital systems are increasingly being used in the ranges of many control engineering. The residue number system offers the possibility of high speed operation and error correction. The compact self-checking pulse-train residue arithmetic circuit is proposed. A fault tolerant digital filter is practically implemented using these proposed circuits.

• 전자공학회논문지A
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• 제33A권10호
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• pp.22-27
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• 1996

A digital logic demodulator for binary FSK signals is presented. The operation is based on the quadricorrelator which is known as an ideal frequency detector. The demodulator is especially suitable for high-speed application, and it can be easily implemented in integrated circuit. Computer simulation results show that the performance of the receiver with digital demodulator converges to that of analog quadricorrelator receiver as the number of mixing axes is increased and the optimum bandwidth depending on a modulation index is slightly wider than that of analog demodulator.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.282-287
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• 1987

This paper presents the development of a microcomputer-aided design program for a digital control system. The program has been written in GWBASIC language which is suitable for Intel 8086II CPU with 640KB memory. By utilizing this program, sampling time, the number of bits A/D and D/A converter, and the stability for the digital control system carl be determined, To demonstrate the utility of this program, a microcomputer controlled precision temperature control system has been employed as an example.

• 한국광학회:학술대회논문집
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• 한국광학회 2006년도 동계학술발표회 논문집
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• pp.335-336
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• 2006

We propose a method of encryption and decryption of binary data using 2-step phase-shifting digital interferometry. This technique reduces the number of interferograms in the phase-shifting interferometry. The binary data has been expressed with random code and random phase. We remove the dc-term of the phase-shifting digital interferogram to restore the original binary data. Simulation results shows that the proposed technique can be used for binary data encryption and decryption.

• 전기학회논문지P
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• 제59권1호
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• pp.1-9
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• 2010

This paper summarizes an education and training system for the auto-reclosing of power transmission system using a real time digital simulator. The system is developed to understand the principle of reclosing and the sequence of automatic reclosing schemes, and practice the effects of reclosing actions to power system in real-time simulator. This study is concentrated into the following two parts. One is the development of real time education and training system of automatic reclosing schemes. For this, we use the RTDS(real time digital simulator) and the actual digital protective relay. The mathematical relay model of RTDS and the actual distance relay which is equipped automatic reclosing function are also used. The other is the user friendly interface between trainee and trainer. The various interface displays are used for user handing and result display. The conditions of automatic reclosing which is a number of reclosing, reclosing dead time, reset time, and so on, can be changed by the user interface panel. A number of scenario cases are reserved for the education and training. Through the test, we verified that the proposed system can be effectively used to accomplish the education and training of automatic reclosing.