• Journal of Advanced Engineering and Technology
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• v.5 no.4
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• pp.349-353
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• 2012

Recently, Mobile multimedia equipments as smart phone and tablet pc requirement is increasing and this market is also being expanded. These mobile equipments require large multi-media function, so more power consumption is required. For these reasons, the needs of power management IC as switching type dc-dc converter and linear regulator have increased. DC-DC buck converter become more important in power management IC because the operating voltage of VLSI system is very low comparing to lithium-ion battery voltage. There are many people to be concerned about digital DC-DC converter without using external passive device recently. Digital controlled DC-DC converter is essential in mobile application to various external circumstance. This paper proposes the DC-DC Buck Converter using the AVR RISC 8-bit micro-processor control. The designed converter receives the input DC 18-30 [V] and the output voltage of DC-DC Converter changes by the feedback circuit using the A/D conversion function. Duty ratio is adjusted to maintain a constant output voltage 12 [V]. Proposed converter using the micro-processor control was compared to a typical boost converter. As a result, the current loss in the proposed converter was reduced about 10.7%. Input voltage and output voltage can be displayed on the LCD display to see the status of the operation.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.11a
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• pp.101-106
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• 1997

Palplus system is a new European 16:9 wide screen TV format which has a full compatibility with standard PAL and the system has a advantage of improving picture quality by the reduction of cross color and cross luminance as well as making use of the full horizontal luminance bandwidth of the PAL system. We implemented European 16:9 PALplus Digital decoder(625/50/2:1) system using SVP(Serial Video Processor) IC and discrete helper demodulator.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.225-228
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• 2004

Digital contents is used already in near place with us. Contents of MPEG-4 standard is used to process multimedia data in field of communication, computer, broadcasting mobile etc. However, absence of copyright management and protection system and interoperability problem of right system between each corporation happened. Because MPEG establish IPMP(Intellectual Property Management and Protection) system standard in agreement with MPEG-4 system standard, proposed cooperation method to manage and protect copyright. Accordingly, in this paper, put in copyright of authorized contents management and protection extension system implementation adding MPEG-4 IPMP system like plug-in into existing MPEG-4 authorizing tool. Therefore, author edits IPMP information to protect contents or object, and process the information in system and authorize MPEG-4 digital contents that have management and protection sign according to IPMP standard. This system designed and implemented to divided into IPMP information save processor, IPMP information creation processor, media IPPM processor, XMT-A to MP4 converter IPMP extension.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.561-564
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• 2009

This paper present design and implementation of U-city infrared image surveillance system based on the digital media processor. The hardware is designed and implemented by using commercial chips such as DM642 processor and video encoder, video decoder and the functions of software are to analyze temperature distribution of a monitoring image and to monitor disaster situation such as fire. The required functions and performances are confirmed by testing of the prototype and we verified practicality of the system.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.1
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• pp.9-12
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• 2010

This paper presents design and implementation of infrared thermal image processing system based on the digital media processor for disaster monitoring. The digital thermal image processing board is designed and implemented by using commercial chips such as DM642 processor and video encoder, video decoder. The implemented functions for disaster monitoring are to analyze temperature distribution of a monitoring infrared thermal image and to detect disaster situation such as fire. For the input of infrared thermal image processing system, an infrared camera of type of the $320\;{\times}\;240\;{\mu}$-bolometer is used. The required functions are confirmed with 10 frame/second of processing performance by testing of the prototype and Practicality of the system was verified.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.59-70
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• 2004

SMT(Simultaneous Multi Threading) architecture uses TLP(Thread Level Parallelism) and increases processor throughput, such that issue slots can be filled with instructions from multiple independent threads. Having multiple ready threads reduces the probability that a functional unit is left idle, which increases processor efficiency. To utilize those advantages for the SMT processors, the issue unit must control the flow of instructions from different threads and not create conflicts among those instructions, which make the SMT issue logic extremely complex. Therefore, our SMT architecture, which is modeled in this paper, uses an in-order-issue and completion scheme, and therefore, can use a simple issue mechanism with a scoreboard already instead of using register renaming or a reorder buffer. However, an SMT scoreboarding mechanism is still more complex and costlier than that of a single threaded conventional processor. This paper proposes an optimal implementation of a scoreboarding mechanism for an ARM-based SMT architecture.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.211-216
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• 2009

As demands for high-definition television (HDTV) increase, the implementation of real-time decoding of high-definition (HD) video becomes an important issue. The data size for HD video is so large that real-time processing of the data is difficult to implement, especially with software. In order to implement a fast moving picture expert group-2 decoder for HDTV, we compose five scenarios that use parallel processing techniques such as data decomposition, task decomposition, and pipelining. Assuming the multi digital signal processor environments, we analyze each scenario in three aspects: decoding speed, L1 memory size, and bandwidth. By comparing the scenarios, we decide the most suitable cases for different situations. We simulate the scenarios in the dual-core and dual-central processing unit environment by using OpenMP and analyze the simulation results.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.8-15
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• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.12
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• pp.31-39
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• 1993

In the playback signal processing of a digital magnetic recording system, the major signal processing processes consist of pulse equalization. pulse detection, clock recovery, and data recovery. Equalizer which compensates interference occurrde between pulses recorded in high density on a magnetic media is realized by pulse slimming method, and pulse detection by a integrating detector. Clock recovery from the detector output was accomplished by using PLL. and data recovery to reduce noise effects was carried out by utilizing the three sampling clocks recovered in clock recovery process. In this paper these processes are implemented in hardware and its performance is evaluated by experimenting with a commercial DAT. It was found that the playback signal processor proposed is suitable to the practical high density magnetic recording system.