• 한국콘텐츠학회논문지
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• 제9권6호
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• pp.45-52
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• 2009

최근 제조업에서 제품 설계를 지원하는 디지털 전문가 시스템을 개발하는 사례가 일어나고 있다. 이 시스템은 제조업에서 엔지니어가 프로세스를 통제하고, 생산관리와 시스템 관리 등을 위하여 사용되고 있다. 본 논문에서는 전문가 시스템을 구축하기 위한 온톨로지 기반의 추론 엔진 개발에 대하여 논한다. 전문가 시스템은 한국어를 지원하고 다양한 기능을 가지며, 그래픽한 온톨로지 맵 인터페이스와 퍼지 룰 기능 정의 등의 기능을 갖도록 하였다. 또한, 온톨로지 맵 구축과 온톨로지 기반의 퍼지 추론 방법에 대하여 지식을 표현하는 방법에 대하여 설명한다.

• 디지털융복합연구
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• 제19권6호
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• pp.315-321
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• 2021

본 연구는 인쇄매체가 영상매체로 재매개 되면서 콘텐츠가 변화되는 과정을 분석한다. 미디어를 통해 콘텐츠가 생산되고, 기존의 콘텐츠가 새로운 미디어에 흡수되면서 변화하는 과정을 관찰하여 재매개된 미디어의 특성을 파악한다. 재매개의 이중논리를 적용하여, 인쇄매체가 영상매체로 재매개되는 과정을 분석하고, 그 결과를 통해 매체의 변화와 변용을 이용한 재매개 방식이 디자인에 방법론에 적용될 수 있다는 가능성을 제시한다. 마블 코믹스는 마블 시네마틱 유니버스로 재매개 되었다. 아날로그 미디어가 새로운 미디어로 재매개되는 현상을 이해함으로써, 디자이너가 디자인을 할 때 재매개의 특성을 이용하여 결과물을 도출 할 수 있도록 디자인 방법론을 제시할 수 있다. 매체가 발달함에 따라 디자인의 범주도 넓어지고 있다. 본 연구를 통해 재매개를 이용한 디자인 방법론 제시되길 기대해 본다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제7권2호
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• pp.143-147
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• 2007

This paper proposes a new watermarking scheme in which a logo watermark is embedded into the discrete wavelet transform (DWT) domain of the original image using exact radial basis function neural networks (RBF). RBF will learn the characteristics of the image, and then watermark is embedded and extracted by the trained RBF. A watermark is added to the coefficients at the low frequency band of the DWT of an image and a watermark is embedded into the DWT domain using the trained RBF. The trained RBF also used in watermark extracting process. Experimental results show that the proposed method has good imperceptibility and high robustness to common image processing attacks.

• ETRI Journal
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• 제26권6호
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• pp.657-660
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• 2004

We propose a fine phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine phase tuner presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO using these techniques show that the noise spectrum and mean square error (MSE) for eight output bits of a 3.125 MHz sine waveform are reduced by 8.68 dB and 5.5 dB, respectively, compared to those of the truncation method, and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1416-1418
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• 2004

This paper proposes an image processing algorithm for detecting obstacles on road-lane using DLI(disparity of lane-related information) that is generated by stereo images acquired from dual cameras mounted on a moving vehicle. The DLI is a disparity that is acquired using single lane information from road lane detection. For the purpose to reduce processing time, we use small blocks obtained by edge-histogram based blocking logic. This algorithm detects moving objects such as preceding vehicles and obstacles. The proposed algorithm has been implemented in a personal computer with the road image data of a typical highway. We successfully performed experiments under a wide variety of road conditions without changing parameter values or adding human intervention. Experimental results also showed that the proposed DLI is quite successful.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.226-229
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• 2000

In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.85-88
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• 2000

In order to resolve problems according to the phase error in QPSK demodulator of the digital communication systems. The demodulator requires carrier recovery loop which searches for the frequency and phase of the carrier. In this paper the complexity of implementation is reduced by the reduction into half of the number of the multiplier in filter structure of the conventional carrier recovery loop, and as the drawback of NCO of the conventional carrier recovery loop wastes a amount of power for the structure of lookup table , We designed the structure of combinational logic without the lookup table. In the comparison with dynamic power of the proposed NCO, the power of NCO with the lookup table is 175㎼, NCO with the proposed structure is 24.65㎼. As the result, it is recognized that about one eight of loss power is reduced. In the simulation of carrier recovery loop designed QPSK demodulator, it is known that the carrier phase is compensated.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 추계학술대회 논문집
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• pp.227-228
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• 2013

The paper is related to smart maximum power system based on program logic. Especially, this system compares the total demand power with the target power by using the signal from the digital kilo watt meter. Based on the power information by the maximum power control equipment the consumed future power is anticipated. In addition, through consumed future power the controllable target power is set, and it applies on the maximum power control equipment. User or manager would control the load efficiently through the simple programming which could control load based on the control sequence and relay. So this system could control load more efficient and stable. Also the conventional load control circuit is not needed. Therefore, it is possible to improve the simple system configuration, which is resulted in cost effective and time saving. So this system is anticipated on time and coast.

• IEIE Transactions on Smart Processing and Computing
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• 제4권5호
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• pp.366-370
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• 2015

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2002년도 춘계학술대회 논문집
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• pp.550-555
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• 2002

In this paper, it is presented a new technique to the design and real-time implementation of fuzzy control system based-on digital signal processors in order to improve the precision and robustness for system of industrial robot. Fuzzy control has emerged as one of the most active and fruitful areas for research in the applications of fuzzy set theory, especially in the real of industrial processes. In this thesis, a self-organizing fuzzy controller or the industrial robot manipulator with a actuator located at the base is studied. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variable of the controller, In the synthesis of a FLC, one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult, SOFC is proposed for a hierarchical control structure consisting of basic level and high level that modify control rules.