• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.2
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• pp.92-99
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• 2014

The paper is related to smart maximum power system based on program logic. Especially, this system compares the total demand power with the target power by using the signal from the digital kilo watt meter. Based on the power information by the maximum power control equipment the consumed future power is anticipated. In addition, through consumed future power the controllable target power is set, and it applies on the maximum power control equipment. User or manager would control the load efficiently through the simple programming which could control load based on the control sequence and relay. To begin with the conventional maximum power control algorithm is surveyed, and the smart maximum power control system based on program logic is used, and the new algorithm from full load to proportion shut down is proposed by using PLC program. the validity of the proposed control scheme is investigated by both simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.1-6
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• 2011

Low-power logic gates, i.e. inverter, NAND, and NOR, are proposed employing only n-channel oxide thin film transistors (TFTs). The proposed circuits were designed to prevent the pull-up and pull-down switches from being turned on simultaneously by using asymmetric feed-through and bootstrapping, thereby exhibited same output voltage swing as the input signal and no static current. The inverter is composed of 5 TFTs and 2 capacitors. The NAND and the NOR gates consist of 10 TFTs and 4 capacitors respectively. The operations of the logic gates were confirmed successfully by SPICE simulation using oxide TFT model.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.4
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• pp.12-17
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• 1976

This paper deals with characteristics and analysis of the Universal Logic Modules as well as TULM, QULM and SULM. Studies are made on minimization in Storms of symmetric circuits and theoretical stuides are made by using the symmetric functions The symmetric circuits of the ULM are realized by employing 54/74 ICs, An oscillator circuit of 10KHz. is constructed based on the ULM. The experimental results gave a good agreement with the theoretical Minimization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.687-688
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• 2011

This paper presents a design method for combinational digital logic systems using time domain based multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• Proceedings of the KAIS Fall Conference
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• 2009.12a
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• pp.636-639
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• 2009

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• ETRI Journal
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• v.29 no.6
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• pp.835-837
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• 2007

A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 ${\mu}m$ CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.3
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• pp.444-450
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• 1996

A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). refs., figs., tabs.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.501-503
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• 1993

A circuit of sigmoid function for neural network is designed by using Piecewise Linear (PWL) method. The slope of sigmoid function can be adjusted to 2 and 0.25. Also the circuit presents both sigmoid function and its differential form. The circuits is simulated by using ViewLogic. Theoretical and simulated performance agree with 1.8 percent.

• ETRI Journal
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• v.26 no.6
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• pp.555-559
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• 2004

We propose an efficient digital IF down converter architecture for dual-mode WCDMA/cdma2000 based on the concept of software defined radio. Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA and cdma2000. A sub-sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi-rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.2
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• pp.115-121
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• 2002

This paper presents an evolutionary design of digital IIR filters using the genetic algorithm (GA) with modified genetic operators and real-valued encoding. Conventional digital IIR filter design methods involve algebraic transformations of the transfer function of an analog low-pass filter (LPF) that satisfies prescribed filter specifications. Other types of frequency-selective digital fillers as high-pass (HPF), band-pass (BPF), and band-stop (BSF) filters are obtained by appropriate transformations of a prototype low-pass filter. In the GA-based digital IIR filter design scheme, filter coefficients are represented as a set of real-valued genes in a chromosome. Each chromosome represents the structure and weights of an individual filter. GA directly finds the coefficients of the desired filter transfer function through genetic search fur given filter specifications of minimum filter order. Crossover and mutation operators are selected to ensure the stability of resulting IIR filters. Other types of filters can be found independently from the filter specifications, not from algebraic transformations.