• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of electromagnetic engineering and science
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• v.4 no.2
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• pp.56-62
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• 2004

We present a multi-Gbit/s digital I/O interface based on RF-modulation and capacitive-coupling over an impedance matched transmission line. The RF-interconnect(RFI) can greatly reduce the digital switching noise and eliminate the dc power dissipation over the channel. It also enables reduced signal amplitude(as low as 200 ㎷) with enhanced data rate and affordable circuit overhead. This paper addresses the system advantages and implementation issues of RFI. A prototype on-chip RFI transceiver is implemented in 0.18-${\mu}{\textrm}{m}$ CMOS. It demonstrates a maximum data rate of 2.2 Gbit/s via 10.5-㎓ RF-modulation. The RFI can be very instrumental for future high-speed inter- and intra-ULSI data links.

• The Journal of the Korea Contents Association
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• v.6 no.2
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• pp.105-116
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• 2006

With the development of IT technology, the amount of digital contents used in various environments of wired/wireless networks have been increased hugely and rapidly To protect the loss of the digital contents from the sudden accident, continuous data backup is required. In this paper, we design and implement the backup system that stores digital contents in backup storage by objectifying the contents with a unit of I/O size and giving them the unique E using the properties of digital contents to avoid duplicated store of the same data. The backup system reduces the amount of backup data efficiently by backing up the only one copy of the duplicated data. as a result, the backup system can back up the digital contents more efficiently in a constrained storage space.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.3 s.94
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• pp.270-276
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• 2005

This paper presents an analytical analysis about neighboring UWB interferences in a S-DMB receiver. We first derive the C/N$_{o}$ of a S-DMB receiver, based on its specifications and present the theoretical description of its effect to UWB interferences in terms of C/(N$_{o}$+ I) and I/N$_{o}$. Using the calculated C/(N$_{o}$+ I) and I/N$_{o}$, we derive the separation distance for a S-DMB receiver not to be interfered by UWB interferences. Finally, we propose an UWB emission limit at minimum separation distance under which a S-DMB is free of UWB interferences and compare it with the value appeared in FCC proposal.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.7
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• pp.636-645
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• 2008

OneNAND flash is a high-performance hybrid flash memory that combines the advantages of both NAND flash and NOR flash. OneNAND flash has not only all virtues of NAND flash but also greatly enhanced read performance which is considered as a downside of NAND flash. As a result, it is widely used in mobile applications such as mobile phones, digital cameras, PMP, and portable game players. However, most of the general purpose operating systems, such as Linux, can not exploit the read performance of OneNAND flash because of the restrictions imposed by their virtual memory system and block I/O architecture. In order to solve that problem, we suggest a new approach called virtual I/O segment. By using virtual I/O segment, the superior read performance of OneNAND flash can be exploited without modifying the existing block I/O architecture and MTD subsystem. Experiments by implementations show that this approach can reduce read latency of OneNAND flash as much as 54%.

• Journal of the Korean Society of Radiology
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• v.11 no.1
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• pp.27-35
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• 2017

The purpose of this study was to investigate the features of CsI:Tl and $Gd_2O_2S$ detectors with an indirect conversion method using phantom in the DR (digital radiography) system by obtaining images of thick chest phantom, medium thickness thigh phantom, and thin hand phantom and by analyzing the SNR and CNR. As a result of measuring the SNR and CNR according to the thickness change of the subject, the SNR and CNR were higher in CsI:Tl detector than in $Gd_2O_2S$ detector when the medium thickness thigh phantom and thin hand phantom were scanned. However, when the thick chest phantom was used, for the SNR at 80~125 kVp and the CNR at 80~110 kVp in the $Gd_2O_2S$ detector, the values were higher than those of CsI:Tl detector. The SNR and CNR both increased as the tube voltage increased. The SNR and CNR of CsI:Tl detector in the medium thickness thigh phantom increased at 40~50 kVp and decreased as the tube voltage increased. The SNR and CNR of $Gd_2O_2S$ detector increased at 40~60 kVp and decreased as the tube voltage increased. The SNR and CNR of CsI:Tl detctor in the thin hand phantom decreased at the low tube voltage and increased as the tube voltage increased, but they decreased again at 100~110 kVp, while the SNR and CNR of $Gd_2O_2S$ detector were found to decrease as the tube voltage increased. The MTF of CsI:Tl detector was 6.02~90.90% higher than that of $Gd_2O_2S$ detector at 0.5~3 lp/mm. The DQE of CsI:Tl detector was 66.67~233.33% higher than that of $Gd_2O_2S$ detector. In conclusion, although the values of CsI:Tl detector were higher than those of $Gd_2O_2S$ detector in the comparison of MTF and DQE, the cheaper $Gd_2O_2S$ detector had higher SNR and CNR than the expensive CsI:Tl detector at a certain tube voltage range in the thick check phantom. At chest X-ray, if the $Gd_2O_2S$ detector is used rather than the CsI:Tl detector, chest images with excellent quality can be obtained, which will be useful for examination. Moreover, price/performance should be considered when determining the detector type from the viewpoint of the user.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2628-2630
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• 2004

In this study, a system that has a high speed digital data I/O and distributive structure is developed and the hardware and software of the system are described in detail. PCI master card to PC slot has maximum 63 slaves which are connected by Ethernet cables and can handle 16 I/O points. The system has some features : easy expansion by adding slaves as needed, space and wiring advantage with distributed characteristics, and select from a range of slave devices that fits best for the use.

• 전자공학회논문지 IE
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• v.43 no.3
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• pp.28-33
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• 2006

In this paper, we consider the input-output(I/O) transformation for the time-varying linear system and get the time-invarying linear system. And we present the necessary sufficient condition for the I/O transformation. The transformed system represent the system with the multiple integral. We verify the proposal algorithm via the example and examine.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.1473-1479
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• 2009

Recently, the high speed train was operated and then the train system's reliability requirements are growing more and more. The exact prediction simulation is necessary in the design of power feeding system by the increase of railway electrification. In order to develope the AC feeding system analysis technology, real-time power simulator was manufactured. It is composed to eight channels analog input, forty channels analog output and forty-eight channels digital I/O. The size of simulator rack is 19" and the two I/O boards are installed the PXI chassis built into the real time os. The signal I/O is possible through BNC connector. The test results of manufactured simulator are obtained that the error range of analog I/O signal is below 1 % and simulation condition is set to 1 ms and the simulation output of the analog output compares the results of the simulator.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.281-283
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• 2016

Recently, many industrial instruments face the problem of protocol compatibility with the external monitoring and control system. This paper is prepared in the main control board to support the industrial communication protocol conversion, control, and monitoring. The industrial communication gateway module is also designed to ensure that the protocol conversion of CAN bus and Ethernet. The main board processor is used the Atmega2560, and placed 4ea RS485 serial slots for sub-board. One of them is used for communication CAN bus and Ethernet. It provides analog and digital I / O through each of the slots is used for control and monitoring.