• 한국멀티미디어학회논문지
• /
• 제22권5호
• /
• pp.527-534
• /
• 2019

Recently, Photo editing softwares such as digital cameras, Paintshop Pro, and Photoshop digital can create counterfeit images easily. Various techniques for detection of tamper images or forgery images have been proposed in the literature. A form of digital forgery is copy-move image forgery. Copy-move is one of the forgeries and is used wherever you need to cover a part of the image to add or remove information. Copy-move image forgery refers to copying a specific area of an image itself and pasting it into another area of the same image. The purpose of copy-move image forgery detection is to detect the same or very similar region image within the original image. In this paper, we proposed fast detection of forgery image using four step search based on discrete cosine transform and a four step search algorithm using discrete cosine transform (FSSDCT). The computational complexity of our algorithm reduced 34.23 % than conventional DCT three step search algorithm (DCTTSS).

• Journal of information and communication convergence engineering
• /
• 제9권5호
• /
• pp.615-618
• /
• 2011

Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.

• 센서학회지
• /
• 제24권3호
• /
• pp.169-174
• /
• 2015

In this study, we developed a system to detect the various defects in the metallic objects using the phenomenon that the defects cause the changes of the natural resonant frequencies. Our system consists of a FFT Amp, an Auto Impact Hammer, a Hammer controller and a PC. Auto Impact Hammer creates vibrations in the metallic objects when tapped on the surface. These vibrational signals are converted to the voltage signals by an acceleration sensor attached to the metallic part surface. These analog voltage signals were fed into an ADC (analog-digital converter) and an FFT (fast fourier transform) conversion in the FFT Amp to obtain the digital data in the frequency domain. Labview graphical program was used to process the digital data from th FFT amp to display the spectrum. We compared those spectra with the standard spectrum to find the shifts in the resonant frequencies of the metal parts, and thus detecting the defects. We used PCB's acceleration sensor and TI's TMS320F28335 DSP (digital signal processor) to obtain the resolution of 2.93 Hz and to analyze the frequencies up to 44 kHz.

• 전력전자학회논문지
• /
• 제12권4호
• /
• pp.339-345
• /
• 2007

본 논문에서는 FPGA(Field Programmable Gate Array) 기반의 전류 제어기를 설계하고 구현하였다. 기존의 DSP(Digital Signal Processor) 기반의 전류 제어기는 알고리즘 연산으로 인해 일반적으로 한 샘플링의 디지털 시지연이 발생한다. 반면에, FPGA 기반의 전류제어기는 FPGA의 높은 연산 능력을 이용하여, 알고리즘 연산에 필요한 시지연을 감소시킬 수 있다. 이로 인해 시지연이 물리적으로 줄기 때문에, 어떠한 시지연 보상 알고리즘 없이 전류 제어기의 대역폭을 향상시킬 수 있다. 구현된 FPGA 기반 전류 제어기의 성능은 실험을 통해 검증되었다.

• 인터넷정보학회논문지
• /
• 제15권2호
• /
• pp.143-147
• /
• 2014

본 논문에서는 디지털 라디오 표준인 DRM(Digital Radio Mondiale) 및 DRM+(Digital Radio Mondiale Plus) 시스템을 이더넷모드에서 분석할 수 있는 다중화분산접속(MDI, Multiplex Distribution Interface) 분석기를 설계한다. 제안하는 MDI 분석기는 메모리 공유 기술을 가진 공통 블록 모듈을 사용하여 MDI 패킷들의 부하를 감소시키며, 차세대 디지털 라디오 방송시스템을 위해 수신된 MDI 패킷을 통해 IP(Internet Protocol)와 DRM/DRM+ 시스템의 FAC(Fast Access Channel)/SDC(Service Description Channel) 구성정보를 확인할 수 있다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
• /
• pp.91-94
• /
• 2000

This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

• 전자공학회논문지B
• /
• 제32B권5호
• /
• pp.661-670
• /
• 1995

This paper presents a fast massively parallel automatic test pattern generator for digital combinational logic circuits using neural networks. Automatic test pattern generation neural network(ATPGNN) evolves its state to a stable local minima by exchanging messages among neural network modules. In preprocessing phase, we calculate the essential assignments for the stuck-at faults in fault list by adopting dominator concept. It makes more neurons be fixed and the system speed up. Consequently. fast test pattern generation is achieved. Test patterns for stuck-open faults are generated through getting initialization patterns for the obtained stuck-at faults in the corresponding ATPGNN.

• 한국음향학회:학술대회논문집
• /
• 한국음향학회 1991년도 학술발표회 논문집
• /
• pp.38-41
• /
• 1991

RLS algorithms are required for applications to adaptive line enhancers, adaptive equalizers for voiceband telephone and HF modems, and wide-badn digital spectrum mobile raio in which their convergence time and tracking speed are significant. The fast QR RLS algorithm satisfies above the requirements. Its computational complexity is linearly proportional to the tap number of a filter, N and its performance remains numerically stable. From the result of simumulation, the fast QR RLS algorithm represented Cioffi is better than gradient based algorithm in its initial performance when being applied to an adaptive line enhancer for cancelling noise.

• 방송공학회논문지
• /
• 제16권5호
• /
• pp.782-792
• /
• 2011

In this paper, we address a new fast DCT-II/DFT/HWT hybrid transform architecture for digital video and fusion mobile handsets based on Jacket-like sparse matrix decomposition. This fast hybrid architecture is consist of source coding standard as MPEG-4, JPEG 2000 and digital filtering discrete Fourier transform, and has two operations: one is block-wise inverse Jacket matrix (BIJM) for DCT-II, and the other is element-wise inverse Jacket matrix (EIJM) for DFT/HWT. They have similar recursive computational fashion, which mean all of them can be decomposed to Kronecker products of an identity Hadamard matrix and a successively lower order sparse matrix. Based on this trait, we can develop a single chip of fast hybrid algorithm architecture for intelligent mobile handsets.

• 지구물리
• /
• 제9권1호
• /
• pp.21-25
• /
• 2006

Aerial photo process with digital camera has some benefits. It is fast and simple by digital way incomparison with aerial photo based on film. Also it works with GPS/INS device to do direct geo-referencing. Sdata and digital map and GCP is produced. In base on it, ortho images are produced and compared with surveying data.