• Title/Summary/Keyword: Digital Fast

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Fast Detection of Forgery Image using Discrete Cosine Transform Four Step Search Algorithm

  • Shin, Yong-Dal;Cho, Yong-Suk
    • Journal of Korea Multimedia Society
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    • v.22 no.5
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    • pp.527-534
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    • 2019
  • Recently, Photo editing softwares such as digital cameras, Paintshop Pro, and Photoshop digital can create counterfeit images easily. Various techniques for detection of tamper images or forgery images have been proposed in the literature. A form of digital forgery is copy-move image forgery. Copy-move is one of the forgeries and is used wherever you need to cover a part of the image to add or remove information. Copy-move image forgery refers to copying a specific area of an image itself and pasting it into another area of the same image. The purpose of copy-move image forgery detection is to detect the same or very similar region image within the original image. In this paper, we proposed fast detection of forgery image using four step search based on discrete cosine transform and a four step search algorithm using discrete cosine transform (FSSDCT). The computational complexity of our algorithm reduced 34.23 % than conventional DCT three step search algorithm (DCTTSS).

A Study on Self Repairing for Fast Fault Recovery in Digital System by Mimicking Cell

  • Kim, Soke-Hwan;Hur, Chang-Wu
    • Journal of information and communication convergence engineering
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    • v.9 no.5
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    • pp.615-618
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    • 2011
  • Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.

Development of the Natural Frequency Analysis System to Examine the Defects of Metal Parts (금속 부품의 결함 판단을 위한 고유 주파수 분석 시스템 개발)

  • Lee, Chung Suk;Kim, Jin Young;Kang, Joonhee
    • Journal of Sensor Science and Technology
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    • v.24 no.3
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    • pp.169-174
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    • 2015
  • In this study, we developed a system to detect the various defects in the metallic objects using the phenomenon that the defects cause the changes of the natural resonant frequencies. Our system consists of a FFT Amp, an Auto Impact Hammer, a Hammer controller and a PC. Auto Impact Hammer creates vibrations in the metallic objects when tapped on the surface. These vibrational signals are converted to the voltage signals by an acceleration sensor attached to the metallic part surface. These analog voltage signals were fed into an ADC (analog-digital converter) and an FFT (fast fourier transform) conversion in the FFT Amp to obtain the digital data in the frequency domain. Labview graphical program was used to process the digital data from th FFT amp to display the spectrum. We compared those spectra with the standard spectrum to find the shifts in the resonant frequencies of the metal parts, and thus detecting the defects. We used PCB's acceleration sensor and TI's TMS320F28335 DSP (digital signal processor) to obtain the resolution of 2.93 Hz and to analyze the frequencies up to 44 kHz.

Implementation of a Fast Current Controller using FPGA (FPGA를 이용한 고속 전류 제어기의 구현)

  • Jung, Eun-Soo;Lee, Hak-Jun;Sul, Seung-Ki
    • The Transactions of the Korean Institute of Power Electronics
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    • v.12 no.4
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    • pp.339-345
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    • 2007
  • This paper presents a design of an FPGA (Field Programmable Gate Array) -based currentcontroller. Using the nature of the high computational capability of FPGA, the digital delay due to the algorithm execution can be reduced. The control performance can be better than the conventional DSP (Digital Signal Processor)-based current controller. Moreover, this method does not need any delay compensation algorithm because the digital delay is physically diminished. Therefore, the bandwidth of the current controller can be extended by this method. The feasibility of this method is verified by several experimental results under the various conditions.

Multiplex Distribution Interface Analyzer Using Memory Sharing Techniqyes on Ethernet Mode for DRM/DRM+ Systems (DRM/DRM+ 이더넷모드의 다중화분산접속 설계분석)

  • Woo, Yongje;Kang, Mingoo;Seo, Jeongwook
    • Journal of Internet Computing and Services
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    • v.15 no.2
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    • pp.143-147
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    • 2014
  • In this paper, a novel MDI(Multiplex Distribution Interface) analyzer is designed in Ethernet-mode for DRM(Digital Radio Mondiale), and DRM+(Digital Radio Mondiale Plus) systems. The proposed MDI analyzer can reduce the overload of MDI packets by using memory sharing techniques into a common module block. In consequence, it verifies the received MDI packets by composition information of IP(Internet Protocol) and FAC(Fast Access Channel)/SDC(Service Description Channel) in DRM/DRM+ systems for the next generation digital radio broadcasting systems.

Low-power, fast-locking All Digital Delay Locked-loop Using Complementary Pass-Transistor Logic (상보형 패스 트랜지스터를 이용한 저전력, 고속력 Delay Locked-Loop 설계)

  • 장홍석;정대영;신경민;정강민
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.91-94
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    • 2000
  • This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

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A Fast Automatic Test Pattern Generator Using Massive Parallelism (대량의 병렬성을 이용한 고속 자동 테스트 패턴 생성기)

  • 김영오;임인칠
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.5
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    • pp.661-670
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    • 1995
  • This paper presents a fast massively parallel automatic test pattern generator for digital combinational logic circuits using neural networks. Automatic test pattern generation neural network(ATPGNN) evolves its state to a stable local minima by exchanging messages among neural network modules. In preprocessing phase, we calculate the essential assignments for the stuck-at faults in fault list by adopting dominator concept. It makes more neurons be fixed and the system speed up. Consequently. fast test pattern generation is achieved. Test patterns for stuck-open faults are generated through getting initialization patterns for the obtained stuck-at faults in the corresponding ATPGNN.

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A Study on the Fast QR RLS Algorithm for Applications to Adaptive Signal Processing (적응 신호 처리에의 응용을 위한 고속 QR RLS 알고리즘의 연구)

  • 정지영
    • Proceedings of the Acoustical Society of Korea Conference
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    • 1991.06a
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    • pp.38-41
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    • 1991
  • RLS algorithms are required for applications to adaptive line enhancers, adaptive equalizers for voiceband telephone and HF modems, and wide-badn digital spectrum mobile raio in which their convergence time and tracking speed are significant. The fast QR RLS algorithm satisfies above the requirements. Its computational complexity is linearly proportional to the tap number of a filter, N and its performance remains numerically stable. From the result of simumulation, the fast QR RLS algorithm represented Cioffi is better than gradient based algorithm in its initial performance when being applied to an adaptive line enhancer for cancelling noise.

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Fast Hybrid Transform: DCT-II/DFT/HWT

  • Xu, Dan-Ping;Shin, Dae-Chol;Duan, Wei;Lee, Moon-Ho
    • Journal of Broadcast Engineering
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    • v.16 no.5
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    • pp.782-792
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    • 2011
  • In this paper, we address a new fast DCT-II/DFT/HWT hybrid transform architecture for digital video and fusion mobile handsets based on Jacket-like sparse matrix decomposition. This fast hybrid architecture is consist of source coding standard as MPEG-4, JPEG 2000 and digital filtering discrete Fourier transform, and has two operations: one is block-wise inverse Jacket matrix (BIJM) for DCT-II, and the other is element-wise inverse Jacket matrix (EIJM) for DFT/HWT. They have similar recursive computational fashion, which mean all of them can be decomposed to Kronecker products of an identity Hadamard matrix and a successively lower order sparse matrix. Based on this trait, we can develop a single chip of fast hybrid algorithm architecture for intelligent mobile handsets.

The Evaluation of the Accuracy of Digital Images according to Exterior-Orientation Methods (외부 표정요소의 취득방법에 따른 디지털 영상의 정확도 평가)

  • Shon, Ho-Woong;Pyo, Ki-Won
    • Journal of the Korean Geophysical Society
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    • v.9 no.1
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    • pp.21-25
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    • 2006
  • Aerial photo process with digital camera has some benefits. It is fast and simple by digital way incomparison with aerial photo based on film. Also it works with GPS/INS device to do direct geo-referencing. Sdata and digital map and GCP is produced. In base on it, ortho images are produced and compared with surveying data.

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