• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• The Journal of the Acoustical Society of Korea
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• v.18 no.3
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• pp.17-26
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• 1999

We present the first speech coarticulation database of Korean, English and Konglish/sup 3)/ named "SORIDA"/sup 4)/, which is designed to cover the maximum number of representations of coarticulation in these languages [1]. SORIDA features a compact database which is designed to contain a maximum number of triphones in a minimum number of prompts. SORIDA contains all consonantal triphones and vowel allophones in 682 Korean prompts of word length and in 717 English prompt words, spoken five times by speakers of balanced genders, dialects and ages. Korean prompts are synthesized lexicons which maximize their coarticulation variation disregarding any stress phenomena, while English prompts are natural words that fully reflect their stress effects with respect to the coarticulation variation. The prompts are designed differently because English phonology has stress while Korean does not. An intermediate language, Konglish has also been modeled by two Korean speakers reading 717 English prompt words. Recording was done in a controlled laboratory environment with an AKG Model C-100 microphone and a Fostex D-5 digital-audio-tape (DAT) recorder. The total recording time lasted four hours. SORIDA CD-ROM is available in one disk of 22.05 kHz sampling rate with a 16 bit sample size. SORIDA digital audio-tapes are available in four 124-minute-tapes of 48 kHz sampling rate. SORIDA′s list of phonetically-rich-words is also available in English and Korean.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.91-97
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• 1995

This paper describes the implementation of a multi-channel audio codec for HETV. This codec has the features of the 3/2-stereo plus low frequency enhancement, downward compatibility with the smaller number of channels, backward compatibility with the existing 2/0-stereo system(MPEG-1 audio), and multilingual capability. The encoder of this codec consists of 6-channel analog audio input part with the sampling rate of 48 kHz, 4-channel digital audio input part and three TMS320C40 /DSPs. The encoder implements multi-channel audio compression using a human perceptual psychoacoustic model, and has the bit rate reduction to 384 kbit/s without impairment of subjective quality. The decoder consists of 6-channel analog audio output part, 4-channel digital audio output part, and two TMS320C40 DSPs for a decoding procedure. The decoder analyzes the bit stream received with bit rate of 384 kbit/s from the encoder and reproduces the multi-channel audio signals for analog and digital outputs. The multi-processing of this audio codec using multiple DSPs is ensured by high speed transfer of date between DSPs through coordinating communication port activities with DMA coprocessors. Finally, some technical considerations are suggested to realize the problem of real-time operation, which are found out through the implementation of this codec using the MPEG-2 layer II sudio coding algorithm and the use of the hardware architecture with commercial multiple DSPs.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.3
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• pp.59-64
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• 2023

Fire and disaster broadcasting systems are divided into analog, digital, and network-based digital public address systems, and important specifications in network-based digital public address systems are low-latency audio, high sampling rate, and multi-channel input and output. In the past, it has been widely used to the AoE method for distinguishing based on the MAC address of the data link layer. However, this method has a problem of increasing complexity and cost. This proposal is an AoIP/UDP method, which allows communication to be easily distinguished by IP address without the need for a separate redundant network, so that the network can be freely used and configured, and cost can be reduced by reducing complexity. After implementing the AoIP/UDP method, the experimental results showed that the cost was improved with the equivalent performance with 2.66ms latency.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.1
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• pp.1-8
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• 2014

Digital watermarking techniques are attracting attention as a proper solution to protect copyright for multimedia data. This paper proposes a new audio watermarking method based on Discrete Cosine Transformation (DCT) and Discrete Wavelet Transformation (DWT) for copyright protection. In our proposed watermarking method, the original audio is transformed into DCT domain and divided into two parts. Synchronization code is applied on the signal in first part and 2 levels DWT domain is applied on the signal in second part. The absolute value of DWT coefficient is divided into arbitrary number of segments and calculates the energy of each segment and middle peak. Watermarks are then embedded into each middle peak. Watermarks are extracted by performing the inverse operation of watermark embedding process. Experimental results show that the hidden watermark data is robust to re-sampling, low-pass filtering, re-quantization, MP3 compression, cropping, echo addition, delay, and pitch shifting, amplitude change. Performance analysis of the proposed scheme shows low error probability rates.

• The Journal of the Acoustical Society of Korea
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• v.21 no.6
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• pp.566-575
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• 2002

Low-titrate audio coding enables a number of Internet and mobile multimedia streaming service more efficiently. For the help of next-generation mobile telephone technologies and digital audio/video compression algorithm, we can enjoy the real-time multimedia contents on our mobile devices (cellular phone, PDA notebook, etc). But the limited available bandwidth of mobile communication network prohibits transmitting high-qualify AV contents. In addition, most bandwidth is assigned to transmit video contents. In this paper, we design a novel and simple method for reproducing high frequency components. The spectrum of high frequency components, which are lost by down-sampling, are modeled by the energy rate with low frequency band in Bark scale, and these values are multiplexed with conventional coded bitstream. At the decoder side, the high frequency components are reconstructed by duplicating with low frequency band spectrum at a rate of decoded energy rates. As a result of segmental SNR and MOS test, we convinced that our proposed method enhances the subjective sound quality only 10%∼20% additional bits. In addition, this proposed method can apply all kinds of frequency domain audio compression algorithms, such as MPEG-1/2, AAC, AC-3, and etc.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.257-258
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• 2006

In this paper, we address several issues in the real time implementation of MPEG-1 Layer II decoder on a fixed-point digital signal processor (DSP), especially TMS320C6416. There is a trade-off between processing speed and the size of program/data memory for the optimal implementation. In a view of the speed optimization, we first convert the floating point operations into fixed point ones with little degradation in audio quality, and then the look-up tables used for the inverse quantization of the audio codec are forced to be located into the internal memory of the DSP. And then, window functions and filter coefficients in the decoder are precalculated and stored as constant, which makes the decoder faster even larger memory size is required. It is shown from the real-time experiments that the fixed-point implementation enables us to make the decoder with a sampling rate of 48 kHz operate with 3 times faster than real-time on TMS320C6416 at a clock rate of 600 MHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.5
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• pp.335-342
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• 2022

In this paper, a single-bit 3rd-order feedforward delta sigma modulator is proposed for audio applications. The proposed modulator is based on a class-C inverter for low voltage and power applications. For the high-precision requirement, the class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier. The proposed Class-C inverter-based modulator is designed and simulated in 180-nm CMOS process. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based switched-capacitor modulator achieves high power efficiency. This design achieves an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.91-97
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• 2004

A digital over-sampling noise-shaping coder to achieve the processing accuracy for the audio signal bandwidth is designed. In order to implement an optimized design of the noise-shaping coder as a form of U (intellectual property), circuit design techniques that optimize the multiplication and the ROM architectures are proposed with emphasis on the low-voltage operation under 2.0 V and the minimization of the hardware resources. In the design and verification methodology, the overall architectures and the internal bit width have been determined through behavioral simulations. The overall performances including timing margin have been estimated through transistor-level simulations. Furthermore, the test results of the implemented chip using a 0.35-${\mu}{\textrm}{m}$ standard CMOS process proposed the validity of the proposed circuits and the design methodology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.