• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.985-988
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• 1999

This paper describes the architecture and the IC implementation of a Direct Digital Frequency Synthesizer (DDFS). That is based on an angle rotation algorithm (CORDIC). It is shown that the architecture can be implemented as a multipliers, feedfoward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 0.35${\mu}{\textrm}{m}$ SAMSUNG KG90 Library.

• 대한설비공학회:학술대회논문집
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• 대한설비공학회 2004년도 하계학술발표 논문집
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• pp.38-38
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• 2004

• 한국디지털건축인테리어학회논문집
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• 제3권2호
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• pp.20-29
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• 2003

It is an obstacle to improve living environments that an acute angle architectural design is often seen. Though that design give a stress to the neighborhood, we can't prevent the design taking place. We must control architectural design, because it is important to public worth and urban aesthetic. To prevent selfish architectural design, it is recommend to extend design review and reflect neighborhood opinions.

• 한국디지털건축인테리어학회논문집
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• 제8권1호
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• pp.81-87
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• 2008

This study is primarily concerned with the relationship between the substantial nature of water and water space, defined as the container of water, when water is used as an element of design. In order to achieve the objective set up, the writer discusses the important properties of water. As the functional meaning of 'water' has been changed to the natural harmony or agreement with human, both the exterior shape of architectural structures and their internal meanings should be taken into account, if the water space is to be suitable for humans.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.491-494
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• 1999

Introduction of digital communication network such as Integrated Services Digital Networks(ISDN) and digital storage media have rapidly developed. Due to a large amount of image data, compression is the key techniques in still image and video using digital signal processing for transmitting and storing. Digital image compression provides solutions for various image applications that represent digital image requiring a large amount of data. In this paper, the proposed DWT(Discrete Wavelet Transform) filter bank is consisted of simple architecture, but it is efficiently designed that a user obtain a wanted compression rate as only input parameter. If it is implemented by FPGA chip, the designed encoder operates in 12MHz.

• 전자공학회논문지 IE
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• 제47권2호
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• pp.1-7
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• 2010

이 논문에서는 PLL에 기반한 주파수 합성기의 구현에 있어서 전력 소모를 줄이기 위한 저전력 디지털 PLL의 구조 및 설계에 대하여 기술한다. 제안된 구조의 디지털 PLL에서는 초기 주파수 비교를 위하여 광대역 디지털 로직 직교상관기를 사용 하고, 최종 주파수 비교를 위하여 저전력 특성을 갖는 협대역 디지털 로직 직교상관기를 사용하여 디지털 제어 발진기의 주파수가 제어되도록 하였다. 또한 동작하지 않는 디지털 블록의 전력을 최소화하는 회로 기법을 적용함으로써 대기 전력 소모를 추가적으로 줄일 수 있도록 하였다. 제안된 디지털 PLL의 동작 및 저전력 특성은 MOSIS 1.8V $0.35{\mu}m$ CMOS 공정 조건에서 MyCAD를 이용한 설계 및 모의실험을 통해 검증하였으며, 20% 정도의 전력 소모 감소 효과를 확인하였다.

• 정보처리학회논문지B
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• 제12B권3호
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• pp.313-322
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• 2005

유비쿼터스 장비를 통해 서버에 있는 디지털 아이템에 접근하기 위해서, 디지털 아이템은 시스템 환경과 장비 특성 및 사용자 선호에 따라 적응되어야한다. 유비쿼터스 환경에서 장비 의존적 적응의 요구 사항은 정적으로 결정되지 않으며 예측할 수 없다. 그러므로 특정한 응용에 대한 적용 절차는 일반적 디지털 아이템 적응 엔진에서 적용될 수 없다. 본 논문에서는 최소의 트랜스코더의 집합과 요구된 적응 요구를 위한 트랜스코딩 경로 생성기, 적응 스케줄러를 갖는 응용-독립적 디지털 아이템 적응 구조를 제안한다. 또한 트랜스코딩 경로인 여러 단위 트랜스코더의 연결을 문맥 자유 문법을 사용하여 찾는 방법을 설명하고, 실험을 하였다.

• ETRI Journal
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• 제35권4호
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• pp.697-705
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• 2013

Emerging trends in the area of digital very large scale integration (VLSI) signal processing can lead to a reduction in the cost of the cochlear implant. Digital signal processing algorithms are repetitively used in speech processors for filtering and encoding operations. The critical paths in these algorithms limit the performance of the speech processors. These algorithms must be transformed to accommodate processors designed to be high speed and have less area and low power. This can be realized by basing the design of the auditory filter banks for the processors on digital VLSI signal processing concepts. By applying a folding algorithm to the second-order digital gammatone filter (GTF), the number of multipliers is reduced from five to one and the number of adders is reduced from three to one, without changing the characteristics of the filter. Folded second-order filter sections are cascaded with three similar structures to realize the eighth-order digital GTF whose response is a close match to the human cochlea response. The silicon area is reduced from twenty to four multipliers and from twelve to four adders by using the folding architecture.

• 한국디지털건축인테리어학회논문집
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• 제13권3호
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• pp.25-32
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• 2013

The elderly in South Korea in 2012 to 11.8% now aging fast-paced world, which is older than most countries. That is, as long as the elderly people lack the time to respond on the issue could cause many problems. According to the principle of social solidarity, long-term care insurance was introduced for the elderly since July 2008 and facility and sanction salaries were supported for the level 1 (the most serious illness) - level 3 (serious illness) elderly. On the other hand, in the fields of architecture, it is difficult to receive the contents of the unified related articles when the design and construction of the elderly welfare facilities take propel commissioned. This paper not only presents the elderly welfare facilities operated according to the institution and policy of elderly welfare facilities in terms of architecture, but also provides the criteria summarized by building facilities in the field of construction of elderly welfare facilities planning, planning, design is intended to provide basic information. This study addresses are as follows: First, the aging population of South Korea and welfare facilities for the elderly are addressed. Second, in terms of architecture, the institution and policy of elderly welfare facilities in South Korea, are addressed. Third, the construction criteria of elderly welfare facilities is summarized to help architectural practitioners understand. Fourth, the future direction of the architectural design of welfare facilities for the elderly is presented.

• 디지털산업정보학회논문지
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• 제11권3호
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• pp.31-43
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• 2015

In this paper, we discuss a code generation technique for custom transport triggered architecture (TTA) from a high-level language structure. This methodology is implemented by using TTA-based Co-design Environment (TCE) tool. The results show how the scheduler exploits instruction level parallelism in the custom target architecture and source program. Thus, the scheduler generates parallel TTA instructions using lower cycle counts than the sequential scheduling algorithm. Moreover, we take Tensilica tool to make a comparison with TCE. Because of the efficiency of TTA, TCE takes less execution cycles compared to Tensilica configurations. Finally, this paper shows that it requires only 7 cycles to generate the parallel TTA instruction set for implementing Cyclic Redundancy Check (CRC) applications as an input design, and presents the code generation technique to move complexity from the processor software to hardware architecture. This method can be applicable lots of channel Codecs like CRC and source Codecs like High Efficiency Video Coding (HEVC).