• KIPS Transactions on Computer and Communication Systems
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• 제8권9호
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• pp.225-230
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• 2019

Recently, with the development of Internet technology, various encryption algorithms have been adopted to protect the sensing data measured by hardware devices. The Advanced Encryption Standard (AES), the most widely used encryption algorithm in the world, is also used in many devices with strong security. However, it has been found that the AES algorithm is vulnerable to side channel analysis attacks such as Differential Power Analysis (DPA) and Correlation Power Analysis (CPA). In this paper, we present a software optimization implementation technique of the AES algorithm applying the most widely known masking technique among side channel analysis attack methods.

• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1053-1063
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• 2017

Power prediction is critical to improve power efficiency in Smart Grids. Markov chain provides a useful tool for power prediction. With careful investigation of practical power datasets, we find an interesting phenomenon that the stochastic property of practical power datasets does not follow the Markov features. This mismatch affects the prediction accuracy if directly using Markov prediction methods. In this paper, we innovatively propose a spatial transform based data processing to alleviate this inconsistency. Furthermore, we propose an enhanced power prediction method, named by Spatial Mapping Markov-Difference (SMMD), to guarantee the prediction accuracy. In particular, SMMD adopts a second prediction adjustment based on the differential data to reduce the stochastic error. Experimental results validate that the proposed SMMD achieves an improvement in terms of the prediction accuracy with respect to state-of-the-art solutions.

• Journal of the Institute of Convergence Signal Processing
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• 제8권3호
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• pp.192-198
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• 2007

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is stored by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). To reduce the ROM size, we use the differential quantization technique with this two ROM. First, we quantize the quarter sine wave with the $2^L$ address and store the quantized value at the Q-ROM. Second, after the $2^L$ address are equally divided into $2^M$ sampling intervals, the sampling value is quantized. And the D-ROM store only the difference between this quantized value and the Q-ROM. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is affected mostly by this ROM reduction.

• Journal of Power Electronics
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• 제18권3호
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• pp.826-840
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• 2018

This paper presents a distributed maximum power point tracking (DMPPT) algorithm based on the reference voltage perturbation (RVP) method for the PV modules of a series PV string. The proposed RVP-DMPPT algorithm is developed to accurately track the maximum power point (MPP) for each PV module operating under all atmospheric conditions with a reduced hardware overhead. To study the influence of parameters such as the controller reference voltage ($V_{ref}$) and PV current ($I_{pv}$) on the PV string voltage, a small signal model of a unidirectional differential power processing (DPP) based PV-Bus architecture is developed. The steady state and dynamic performances of the proposed RVP DMPPT algorithm and small signal model of the unidirectional DPP based PV-Bus architecture are demonstrated with simulations and experimental results. The accuracy of the RVP DMPPT algorithm is demonstrated by obtaining a tracking efficiency of 99.4% from the experiment.

• Proceedings of the KIPE Conference
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.247-249
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• 2007

This paper proposes a dry-type surface myoelectric sensor for the myoelectric hand prosthesis. The designed surface myoelectric sensor is composed of skin interface and processing circuits. The skin interface has one reference and two input electrodes, and the reference electrode is located in the center of two input electrodes. Considering the conduction velocity and the median frequency of the myoelectric signal, the inter-electrode distance (IED) between two input electrodes as 18mm, 20mm, and 22mm is selected. The signal processing circuit consists of a differential amplifier with a band pass filter, a band rejection filter for rejecting 60㎐ power-line noise, amplifier, and a level circuit. Using SUS440, six prototype skin interface with different reference electrode shape and IED is fabricated, and their output characteristics are evaluated by output signal obtained from the forearm of a healthy subject. The experimental results show that the skin interface with parallel bar shape and the 18mm IED has a good output characteristics. The fabricated dry-type surface myoelectric sensor is evaluated for the upper-limb amputee.

• Journal of the Institute of Convergence Signal Processing
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• 제16권1호
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• pp.29-34
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• 2015

The ECG(Electrocardiograph) ambulatory test as called Holter is performed usually to diagnose several heart diseases causing different arrhythmias. This paper exposes the insights of the design of a 10-lead ambulatory ECG recorder. Reducing the size and minimizing the power consumption of the ECG recorder are crucial to allow long recording time without causing discomfort to the patient. This paper proposes lower hardware design and differential compression algorithm to extend the maximum 72 hours recording time in consideration of smaller and light-weighted recorder size. The performance results by newly introduced compression algorithm are shown and discussed.

• Proceedings of the Korea Information Processing Society Conference
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• 한국정보처리학회 2019년도 춘계학술발표대회
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• pp.125-128
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• 2019

최근 사물인터넷 기술의 발전과 함께 하드웨어 디바이스에서 측정하는 센싱 데이터를 보호하기 위해 다양한 방식의 암호화 알고리즘을 채택하고 있다. 그 중 전 세계에서 가장 많이 사용하는 암호화 알고리즘인 AES(Advanced Encryption Standard) 또한 강력한 안전성을 바탕으로 많은 디바이스에서 사용되고 있다. 하지만 AES 알고리즘은 DPA(Differential Power Analysis), CPA(Correlation Power Analysis) 같은 부채널 분석 공격에 취약하다는 점이 발견되었다. 본 논문에서는 부채널 분석 공격대응방법 중 가장 널리 알려진 마스킹 기법을 적용한 AES 알고리즘의 소프트웨어 최적화 구현 기법을 제시한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• 제31권6호
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• pp.1127-1136
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• 2021

In the field of power analysis attacks, electrical noise and misalignment of the power consumption trace are the major factors that determine the success of the attack. Therefore, several studies have been conducted to overcome this problem, and one of them is a signal processing method based on wavelet transform. Up to now, discrete wavelet transform, which can compress the trace, has been mostly used for power side-channel power analysis because continuous wavelet transform techniques increase data size and analysis time, and there is no efficient scale selection method. In this paper, we propose an efficient scale selection method optimized for power analysis attacks. Furthermore, we show that the analysis performance can be greatly improved when using the proposed method. As a result of the CPA(Correlation Power Analysis) and DDLA(Differential Deep Learning Analysis) experiments, which are non-profiling attacks, we confirmed that the proposed method is effective for noise reduction and trace alignment.

• Proceedings of the KIPE Conference
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• 전력전자학회 2014년도 추계학술대회 논문집
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• pp.46-47
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• 2014

본 논문은 태양광 발전 시스템 중 차동 전력 조절기가 다루는 전력을 최소화하기 위한 LPPT (Least Power Point Tracking) 에 관한 것이다. 두 개 이상의 태양광 모듈에서 그늘짐 등으로 인해 발생 하는 전력 차이를 양방향 차동 전력 조절기를 통해 다루게 되는데, 이 때 태양광 모듈을 입력으로 하는 부스트 컨버터의 스트링 전류를 조절하게 되면 차동 전력 조절기가 담당하는 전력이 최소가 되도록 할 수 있다. 차동 전력 조절기의 용량이 줄어듦에 따라 시스템 크기를 줄일 수 있고, 이와 함께 단가도 감소하는 효과를 낼 수 있다. 본 논문에서는 차동 전력 조절기의 전력이 최소가 되게 하는 LPPT 방법을 PSIM 시뮬레이션과 실험을 통해 입증 하고자 한다.

• Journal of the Korean Institute of Telematics and Electronics C
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• 제34C권6호
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.