• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.31-32
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• 2015

본 논문에서는 전하 균등화를 해주는 동시에 차동전력조절 방식(Differential Power Processing, DPP)을 추가하여 최대 전력점(Maximum Power Point, MPP)을 추종하는 회로를 제안한다. 이를 통하여 본 논문에서는 PV모듈을 제어를 하고, 동시에 벅-플라이백 컨버터를 이용하여 전하 균등화를 할 수 있다. 본 논문에서의 전력조절기는 포워드컨버터로 구성 되어 있고, 주 컨버터인 전하균등화회로는 벅-플라이백컨버터로 구성하였다. 컨버터의 입력은 PV모듈을 직렬로 연결, 출력은 배터리를 직렬로 연결하여 제안한 기능을 구현하였다. 이에 따른 조건을 수식으로 증명하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.685-695
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• 1997

In this paper, a new CMOS continuous-time fully-differential current-mode integrator is proposed as a basic building block of the low-voltage high frequency current-mode active filter. The proposed integrator is composed of the CMOS complementary circuit which can extend transconductance of an integrator. Therefore, the unity gain frequency which is determined by a small-signal transconductance and a MOSFET gate capacitance can be expanded by the complementary transconductance of the proposed integrator. And also the magnitude of pole and zero are increased. The unity gain frequency of the proposed integrator is increased about two times larger than that of the conventional continuous-time fully-differential integrator with NMOS-gm. These results are verified by the small signal analysis and the SPICE simulation. As an application circuit of the proposed fully-differential current-mode integrator, the three-pole Chebyshev lowpass filter is designed using 0.8.$\mu$m CMOS processing parameters. SPICE simulation predicts a 3-dB bandwidth of 148MHz and power dissipation of 4.3mW/pole for the three-pole filter with 3-V power supply.

• Journal of the Korean Society for Nondestructive Testing
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• v.25 no.6
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• pp.439-445
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• 2005

The stud bolt is one of crucial parts for safe operation of reactor vessels in nuclear power plants, Crack initiation and propagation were reported in stud bolts that arc used for closure of reactor vessel and head, Stud bolts are inspected by ultrasonic technique during overhaul periodically for the prevention of stud bolt failure which could induce radioactive leakage from nuclear reactor, In conventional ultrasonic testing for inspection of stud bolts, cracks are detected by using shadow effect It takes too much time to inspect stud bolts by using conventional ultrasonic technique. In addition, there were numerous spurious signals reflected from every oblique surfaces of thread, In this study, the signal processing technique for enhancing conventional ultrasonic technique was introduced for inspecting stud bolts. The signal processing technique provides removing spurious signal reflected from every oblique surfaces of thread and enhances detectability of defects. Detectability for small crack was enhanced by using this signal processing in ultrasonic inspection of stud bolts in Nuclear Power Plants.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.05a
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• pp.671-674
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• 2013

단순전력분석(Simple Power Analysis, SPA)은 적은 수의 평문으로 암호 알고리즘에 대한 패턴 뿐만 아니라 비밀키의 정보를 찾는 전력 분석(Power Analysis)의 방법 중 하나이다. SPA의 장점은 차분전력분석(Differential Power Analysis, DPA) 또는 상관전력분석(Correlation Power Analysis, CPA)보다 적은 계산량으로 비밀키 분석을 할 수 있고, DPA 또는 CPA 분석을 하기 위해 필요한 분석위치 탐지에 효율적으로 활용이 되어 진다는 것이다. 하지만 최근 SPA 분석 성능을 저하시키기 위해 클락 노이즈, 전력 노이즈, 딜레이 노이즈 등 다양한 방법들이 제안되어지고 있다. 본 논문에서는 다양한 노이즈가 있는 환경에서 아날로그 수신기를 활용하여 특정 주파수 영역을 필터링한 후 노이즈를 제거하는 방법을 소개한다. 실험을 통해, 아날로그 수신기를 사용하였을 경우에 사용하지 않았을 경우보다 뚜렷한 대칭키 암호의 라운드 함수가 구분되어지며, 라운드 내 함수 구분도 가능함을 보인다. 이는 DPA 또는 CPA를 이용하여 분석을 수행하고자 할 때 분석 위치를 결정하데 아주 유용하게 활용되어지며, 분석 성능향상에도 기여할 것으로 기대되어진다.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.33-41
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• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.183-188
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• 2015

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with $0.18{\mu}m$ complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.2
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• pp.37-44
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• 2002

In this paper, the Viterbi decoder containing new branch metrics of the squared Euclidean distance with multiple order phase differences is introduced in order to improve the bit error rate (BER) in the differential detection of the trellis-coded MDPSK-DFDM. The proposed Viterbi decoder is conceptually same as the sliding multiple phase differential detection method that uses the branch metric with multiple phase differences. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER peformance without sacrificing bandwidth and power efficiency. Also, the proposed algorithm can be used in the single carrier modulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.38-49
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• 1998

A fossil power plant can be modeled by a lot of algebraic equations and differential equations. When we simulate a large, complicated fossil power plant by a computer such as workstation or PC, it takes much time until overall equations are completely calculated. Therefore, new processing systems which have high computing speed is ultimately needed for real-time or high-speed(faster than real-time) simulators. This paper presents an enhanced strategy in which high computing power can be provided by parallel processing of DSP processors with communication links. DSP system is designed for general purpose. Parallel DSP system can be easily expanded by just connecting new DSP modules to the system. General urpose DSP modules and a VME interface module was developed. New model and techniques for the task allocation are also presented which take into account the special characteristics of parallel I/O and computation. As a realistic cost function of task allocation, we suggested 'simulation period' which represents the period of simulation output intervals. Based on the development of parallel DSP system and realistic task allocation techniques, we cound achieve good efficiency of parallel processing and faster simulation speed than real-time.

• ETRI Journal
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• v.31 no.6
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• pp.717-724
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• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.