• International Journal of Advanced Culture Technology
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• v.6 no.3
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• pp.187-192
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• 2018

Permeate alteration technique is compounded the steeple sway-tuner status of the gleam-differential realization level (GDRL) on the permeate realization morph. The realization level condition by the permeate realization morph system is associated with the sway-tuner system. As to search a dot of the dot situation, we are gained of the permeate value with character-dot by the output signal. The concept of realization level is composed the reference of gleam-differential level for alteration signal by the permeate tuner morph. Moreover displaying a steeple alteration of the GDRL of the average in terms of the sway-tuner morph, and permeate dot tuner that was the a permeate value of the far alteration of the $Per-rm-FA-{\alpha}_{AVG}$ with $14.63{\pm}1.23units$, that was the a permeate value of the convenient alteration of the $Per-rm-CO-{\alpha}_{AVG}$ with $8.28{\pm}0.97units$, that was the a permeate value of the flank alteration of the $Per-rm-FL-{\alpha}_{AVG}$ with $3.28{\pm}0.58units$, that was the a permeate value of the vicinage alteration of the $Per-rm-VI-{\alpha}_{AVG}$ with $0.51{\pm}0.10units$. The sway tuner will be to evaluate at the steeple ability of the sway-tuner morph with character-dot by the permeate realization level on the GDRL that is displayed the gleam-differential morph by the realization level system. Sway realization system will be possible to control of a morph by the special signal and to use a permeate data of sway tuner level.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.4 s.310
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• pp.53-59
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• 2006

This paper describes the new design technique of full wave rectifier (FWR) for precise measurement instrument and the chip implementation of this FWR circuit with measurement results. Conventional circuits have some problems of complex design and limited output range( $VDD/2{\sim}VLIIV1IT+$). Proposed FWR circuit was simply designed with two 2x1 MUXs, one high speed comparator, and one differential difference amplifier(DDA). One rail-to-rail differential difference amplifier(DDA) performs the DC level shifting to VSS and 2X amplification simultaneously, and enables the full range ($Vss{\sim}VDD$) operation. The proposed FWR circuits shows more than 50% reduction of chip area and power consumption compared to conventional one. Proposed circuit was implemented with 0.35um 1-poly 2-metal CMOS process. Core size is $150um{\times}450um$ and power dissipation is 840uW with 3.3V single supply.

• Journal of IKEEE
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• v.14 no.1
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• pp.8-16
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• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.964-969
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• 2007

A regulated low phase noise differential colpitts VCO(Voltage Controlled Oscillator) for mobile RFID system is presented. The differential colpitts VCO meets the dense reader environment specifications. The VCO use a $0.35{\mu}m$ technology and achieves tuning range $1.55{sim}2.053 GHz$. Measuring 910 MHz frequency divider output, phase noise performance is -106 dBcMz and -135dBc/Hz at 40 kHz and 1MHz offset, respectively. 5-bit digital coarse-tuning and accumulation type MOS varactors allow for 28.2% tuning range, which is required to cover the LO frequency range of a UHF Mobile RFID system, Optimum design techniques ensure low VCO gain(<45 MHz/V) for good interoperability with the frequency synthesizer. To the author' knowledge, this differential colpitts VCO achieves a figure of merit(FOM) of 1.93dB at 2-GHz band.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.14-17
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• 2008

This paper describes the simulation of a phase splitter for the design of Chireix Outphasing power amplifier. Phase splitter separate the input signal with $0[^{\circ}]$ into the signal with $+90[^{\circ}]$ and $-90[^{\circ}]$ Chireix Outphasing power amplifier get a linearized output from the signal amplifying and combining the separated signal with the phase of $+90[^{\circ}]$ and $-90[^{\circ}]$ of the phase splitter. phase splitter is the core device when designing Chireix Outphasing power amplifier. It is very difficult to design phase splitter with the difference of $90[^{\circ}]$. This phase splitter is used to design the difference of $180[^{\circ}]((90[^{\circ}]+{\alpha}),\;-(90[^{\circ}])+{\alpha}))$ using simulation tool and a differential amplifier.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.38 no.6
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• pp.475-482
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• 2014

This paper presents the results of an experimental feasibility study on low-temperature differential Stirling engines with water spray heat transfer. The water spray enhances the efficiency of the heat transfer from heat sources to the engine and reduces the performance degeneration due to the dead volumes of conventional heat exchangers. A test Stirling engine was developed and an experiment was conducted to determine the characteristics for the initial start-up, steady-state operation, and power output for various flow rates and temperatures of hot supply water. The test results showed that larger flow rates led to reductions in the minimum working temperature of the hot water at start-up. During a series of steady-state operations, higher flow rates and temperatures increased the working speed. Furthermore, the work per cycle and power output were also increased. Eventually, the test Stirling engine had a power level of 0.05 W. Based on this, further research will be conducted to obtain a higher power output and investigate various applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.94-100
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• 2014

In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• Journal of Sensor Science and Technology
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• v.29 no.5
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• pp.303-311
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• 2020

Nondispersive infrared CO₂ gas sensor was developed after the simulation of optical cavity structure and assembling the optical components: IR source, concave reflectors, Fresnel lens, a hollow disk, and IR detectors. By placing a hollow disk in front of reference IR detector, the output voltages are almost constant value, near to 70.2 mV. The absorbance of IR light, F_a, shows the second order of polynomial according to ambient temperatures at 1,500 ppm. The differential output voltages and the absorbance of IR light give a higher accuracy in estimations of CO₂ concentrations with less than ± 1.5 % errors. After implementing the parameters that are dependent upon the ambient temperatures in microcontroller unit (MCU), the measured CO₂ concentrations show high accuracies (less than ± 1.0 %) from 281 K to 308 K and the time constant of developed sensor is about 58 sec at 301 K. Even though the estimation errors are relatively high at low concentration, the developed sensor is competitive to the commercial product with a high accuracy and the stability.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1666-1671
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• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.