• Journal of Korea Multimedia Society
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• v.18 no.3
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• pp.401-407
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• 2015

In this paper, we propose the method to eliminate EMI (Electro-Magnetic Interference) in ELF (Extremely Low Frequency) band below 2 KHz for extending the gesture-recognition distance of smart TVs to more than 3m using electric potential sensor. First, we measure the electric field generated from the back panel of a TV and propose the effective arrangement of two sets of differential sensors as well as the shielding method using metal fiber. Also, we eliminate the PLN (Power Line Noise) and other noise generated from the TV and sensors as well as surrounding environments using filters. Using the proposed EMI eliminating methods, we evaluate displacement ratio on measured signals according to distance between sensors and a moving hand. Experiment results show that our proposed method can extend the hand-gesture sensing distance using EPS (Electric Potential Sensor) up to more than 3m, which is enough to satisfy applicability of EPS based remote control to Smart TVs.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.22 no.10
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• pp.687-696
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• 2010

In this study, FDD algorithm was developed using the normalized distance method and general pattern classifier method that can be applied to constant air volume air handling unit(CAV AHU) system. The simulation model using TRNSYS and EES was developed in order to obtain characteristic data of CAV AHU system under the normal and the faulty operation. Sensitivity analysis of fault detection was carried out with respect to fault progress. When differential pressure of mixed air filter increased by more than about 105 pascal, FDD algorithm was able to detect the fault. The return air temperature is very important measurement parameter controlling cooling capacity. Therefore, it is important to detect measurement error of the return air temperature. Measurement error of the return air temperature sensor can be detected at below $1.2^{\circ}C$ by FDD algorithm. FDD algorithm developed in this study was found to indicate each failure modes accurately.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.587-591
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• 2001

This paper deals with inspect algorithm using visual system. One of the major problems that arise during polymer production is the estimation of the noise of the color product.(bad pallets) An erroneous output can cause a lot of losses (production and financial losses). Therefore new methods for real-time inspection of the noise are demanded. For this reason, we have presented a development of vision system algorithm for the defect inspection of PE color pallets. First of all, in order to detect the edge of object, the differential filter is used. And we apply to the labelling algorithm for feature extraction. This algorithm is designed for the defect inspection of pallets. The labelling algorithm permits to separate all of the connected components appearing on the pallets. Labelling the connected regions of a image is a fundamental computation in image analysis and machine vision, with a large number of application. Also, we suggested vision processing program in window environment. Simulations and experimental results demonstrate the performance of the proposal algorithm.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.1
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• pp.35-40
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• 2015

Generators are the most complex and expensive single element in a power system. The generator protection relays should to minimize damage during fault states and must be designed for maximum reliability. A conventional CDR(Current Differential Relaying) technique based on DFT(Discrete Fourier Transform) filter have the disadvantages that the time information can lead to loss in the process of converting the signal from the time domain to the frequency domain. A WT(Wavelet transform) and WT analysis is known that it is possible with the local analysis of the fault and transient signal. In this paper, to overcome the defects in the DFT process, an application of WT for fault detection of generator is presented. This paper describes an selection of mother Wavelet to detect faults of generator. Using collected data from the fault simulation with ATPdraw, we analyzed the several mother Wavelet through the course of MLD(multi-level decomposition) using MATLAB software. Finally, it can be seen that the proposed technique using detail coefficient of Daubechies level 2 which can be fault discriminant of generator.

• ETRI Journal
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• v.30 no.4
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• pp.526-534
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• 2008

This paper presents a fully integrated 0.13 ${\mu}m$ CMOS MB-OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low-pass filter, a variable gain amplifier, a voltage-to-current converter, an I/Q up-mixer, a differential-to-single-ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 ${\mu}m$ CMOS technology. The fabricated transmitter shows a -3 dB bandwidth of 550 MHz at each sub-band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.

• Journal of Korea Society of Industrial Information Systems
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• v.13 no.1
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• pp.57-67
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• 2008

In this paper, we present an adaptive block matching motion estimation using optical flow. In the proposed algorithm, we calculate the temporal and spatial gradient value for each pixel value from tile differential filter, and estimate the optical flow which is used to decide the location and the size of the search region from the gradient values by least square optical flow algorithm. In particular, the proposed algorithm showed a excellent performance with fast and complex motion sequences. From the computer simulation for various motion characteristic sequences. The proposed algorithm shows a significant enhancement of PSNR over previous blocking matching algorithms.

• Journal of Sensor Science and Technology
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• v.28 no.4
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• pp.240-245
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• 2019

Phase interpolation is widely adopted in frequency synthesizers and clock-and-data recovery systems to produce an intermediate phase from two existing phases. The intermediate phase is typically generated by combining two input phases with different weights. Unfortunately, this results in non-uniform phase steps. Alternatively, the intermediate phase can be generated by successive approximation, where the interpolated phase at each approximation stage is obtained using the same weight for the two intermediate phases. As a proof of concept, this study presents a 2-GHz 8-bit successive approximation digital-to-phase converter that is designed using 65-nm CMOS technology. The converter receives an 8-phase clock signal as input, and the most significant bit (MSB) section selects four phases to create two sinusoidal waveforms using a harmonic rejection filter. The remaining least significant bit (LSB) section applies the successive approximation to generate the required intermediate phase. Monte-Carlo simulations show that the proposed converter exhibits 0.46-LSB integral nonlinearity and 0.31-LSB differential nonlinearity with a power consumption of 3.12 mW from a 1.2-V supply voltage.

• Transactions of the Korean hydrogen and new energy society
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• v.34 no.1
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• pp.17-25
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• 2023

The purpose of this study was to propose a design that shows optimal performance by changing the geometry of the internal flow path of the receptacle in order to prevent the decrease in flow rate and differential pressure performance due to the application of the receptacle in the hydrogen charging system. To achieve this, 3D computational fluid dynamics simulation was performed for the receptacle, according to the geometry of the flow path inside the receptacle. The pressure results at the inlet and outlet were measured the same as both of N and H₂ in the experiment, and the flow rate of H₂ was 3.75 times higher than that of N₂. In addition, since the flow performance of the receptacle improved under conditions where the flow path was widened, it was confirmed that reducing the diameter of the poppet and the width of the guide are advantageous for improving performance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.2
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• pp.143-148
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• 2022

For the purpose of treating health checkups and recovery of patients in a super-aged society, hospitals use devices designed with a reduction circuit of electromagnetic waves associated with the specific absorption rate of electromagnetic waves absorbed by the human body. In this paper, we proposed a filter improvement design method capable of reducing electromagnetic waves. As a result of confirming the validity of the proposed technique through simulation and experimental results, the following result values were obtained. Applying the common-mode (CM) inductor 4 mH to a calibration circuit, noise decreased in a multiband spectrum. Using the differential mode(DM) inductor 40 µH element in the primary calibration circuit, the noise decreased by 15 dB or more in the 3 MHz band spectrum. Also, applying the Admittance Capacitance (Y-Cap) 10 nF element in the secondary calibration circuit resulted in the decrease by more than 30 dB in the band spectrum before 2 MHz. After using a common-mode inductor 4 mH element in the tertiary calibration circuit, it decreased by more than 15 dB in the band spectrum after 2 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.