• Journal of Powder Materials
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• v.31 no.2
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• pp.132-136
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• 2024

This study investigated the effects of revolution speed and ball size in planetary milling on the microstructure and dehydrogenation behavior of TiH₂ powder. The particle size analysis showed that the large particles present in the raw powder were effectively refined as the revolution speed increased, and when milled at 500 rpm, the median particle size was 1.47 ㎛. Milling with a mixture of balls of two or three sizes was more effective in refining the raw powder than milling with balls of a single size. A mixture of 3 mm and 5 mm diameter balls was the optimal condition for particle refinement, and the measured median particle size was 0.71 ㎛. The dependence of particle size on revolution speed and ball size was explained by changes in input energy and the number of contact points of the balls. In the milled powder, the endothermic peak measured using differential thermal analysis was observed at a relatively low temperature. This finding was interpreted as the activation of a dehydrogenation reaction, mainly due to the increase in the specific surface area and the concentration of lattice defects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Journal of the Korea institute for structural maintenance and inspection
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• v.27 no.2
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• pp.17-24
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• 2023

A post-processing technique for the measurement signal of a solenoid-type sensor is introduced. The solenoid-type sensor nondestructively evaluates an external tendon of prestressed concrete using the total flux leakage (TFL) method. The TFL solenoid sensor consists of primary and secondary coils. AC electricity, with the shape of a sinusoidal function, is input in the primary coil. The signal proportional to the differential of the input is induced in the secondary coil. Because the amplitude of the induced signal is proportional to the cross-sectional area of the tendon, sectional loss of the tendon caused by ruptures or corrosion can be identified by the induced signal. Therefore, it is important to extract amplitude information from the measurement signal of the TFL sensor. Previously, the amplitude was extracted using local maxima, which is the simplest way to obtain amplitude information. However, because the sampling rate is dramatically decreased by amplitude extraction using the local maxima, the previous method places many restrictions on the direction of TFL sensor development, such as applying additional signal processing and/or artificial intelligence. Meanwhile, the proposed method uses amplitude demodulation to obtain the signal amplitude from the TFL sensor, and the sampling rate of the amplitude information is same to the raw TFL sensor data. The proposed method using amplitude demodulation provides ample freedom for development by eliminating restrictions on the first coil input frequency of the TFL sensor and the speed of applying the sensor to external tension. It also maintains a high measurement sampling rate, providing advantages for utilizing additional signal processing or artificial intelligence. The proposed method was validated through experiments, and the advantages were verified through comparison with the previous method. For example, in this study the amplitudes extracted by amplitude demodulation provided a sampling rate 100 times greater than those of the previous method. There may be differences depending on the given situation and specific equipment settings; however, in most cases, extracting amplitude information using amplitude demodulation yields more satisfactory results than previous methods.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.5
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• pp.619-628
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• 2010

Shape Memory Alloy (SMA) has recently received attention in developing implantable surgical equipments and it is expected to lead the future medical device market by adequately imitating surgeons' flexible and delicate hand movement. However, SMA actuators have not been used widely because of their nonlinear behavior called hysteresis, which makes their control difficult. Hence, we propose a parameter, $t_1$, which is necessary for temperature control, by analyzing the open-loop step response between current and temperature and by comparing it with the values of linear differential equations. $t_1$ is a pole of the transfer function in the invariant linear model in which the input and output are current and temperature, respectively; hence, $t_1$ is found to be related to the state variable used for temperature control. When considering the parameter under heat treatment conditions, $T_{max}$ was found to assume the lowest value, and $t_1$ was irrelevant to the heat treatment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.53-60
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• 2004

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.195-201
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• 2014

In this study, face recognition system was designed based on polynomial Radial Basis Function Neural Networks(pRBFNNs) pattern classifier using 2-directional 2-dimensional principal component analysis algorithm. Existing one dimensional PCA leads to the reduction of dimension of image expressed by the multiplication of rows and columns. However $(2D)^2PCA$(2-Directional 2-Dimensional Principal Components Analysis) is conducted to reduce dimension to each row and column of image. and then the proposed intelligent pattern classifier evaluates performance using reduced images. The proposed pRBFNNs consist of three functional modules such as the condition part, the conclusion part, and the inference part. In the condition part of fuzzy rules, input space is partitioned with the aid of fuzzy c-means clustering. In the conclusion part of rules. the connection weight of RBFNNs is represented as the linear type of polynomial. The essential design parameters (including the number of inputs and fuzzification coefficient) of the networks are optimized by means of Differential Evolution. Using Yale and AT&T dataset widely used in face recognition, the recognition rate is obtained and evaluated. Additionally IC&CI Lab dataset is experimented with for performance evaluation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1061-1068
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• 2017

A RVDT is a sensor that measures angular displacement and the output signal of RVDT is a DSBSC-AM signal. For this reason, a DSBSC-AM demodulation processor is required to determine the angular displacement from the output signal. In this paper, DADC(Digital Angle to DC) which extracts the angular displacement from the output signal of a RVDT is implemented based-on modified Costas Loop usually used in the demodulation of DSBSC-AM signal by using FPGA. DADC can used with both 4-wire and 5-wire RVDTs and can exactly compensate the phase difference between the input excitation and output signals of a RVDT unlike the conventional analog RVDT signal conditioners which require external components. Since digital signal processing technique that can enhance the linearity is exploited, DADC shows 0.035% linearity error, which is smaller than 0.005% that of a conventional analog signal conditioner. The DADC are tested in an integrated experimental environment which includes a commercial RVDT sensor, ADC and an analog output block.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1303-1310
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• 2016

In this paper, electrocardiogram (ECG) analog front end with supply voltage of 0.5V has been designed and verified by measurements of fabricated chip. ECG is composed of instrument amplifier, 6th order gm-C low pass filter and variable gain amplifier. The instrument amplifier is designed to have gain of 34.8dB and the 6th order gm-C low pass filter is designed to obtain the cutoff frequency of 400Hz. The operational transconductance amplifier of the low pass filter utilizes body-driven differential input stage for low voltage operation. The variable gain amplifier is designed to have gain of 6.1~26.4dB. The electrocardiogram analog front end are fabricated in TSMC $0.18{\mu}m$ CMOS process with chip size of $858{\mu}m{\times}580{\mu}m$. Measurements of the fabricated chip is done not to saturate the gain of ECG by changing the external resistor and measured gain of 28.7dB and cutoff frequency of 0.5 - 630Hz are obtained using the supply voltage of 0.5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.13-20
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• 2008

This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.