• Title/Summary/Keyword: Difference Circuits

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High Noise Margin LVDS I/O Circuits for Highly Parallel I/O Environments (다수의 병렬 입.출력 환경을 위한 높은 노이즈 마진을 갖는 LVDS I/O 회로)

  • Kim, Dong-Gu;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.1
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    • pp.85-93
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    • 2007
  • This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

Miniaturized Development of Microwave Power Divider Using High-Tc Superconductors (고온초전도체를 이용한 마이크로파 전력분배기의 소형화 개발)

  • Chung, Dong-Chul;Yoo, Byung-Hwa;Kwak, Min-Hwan;Kang, Gwang-Yong;Han, Byoung-Sung
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.58 no.3
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    • pp.334-338
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    • 2009
  • In this paper, We report the miniaturization of superconducting microwave power dividers based on lumped element equivalent circuits. To do this, we analyzed a conventional branch-type power divider by using an ABCD matrix under even and odd mode excitation. Then, we calculated each lumped element impedance throughout this analysis of a transmission line matrix. Also we simulated our equivalent circuits made of lumped elements by using a full wave analysis, em Sonnet. Our deign of microwave power divider based on simulated results was fabricated on high-$T_c$ superconducting thin films deposited on MgO substrate. Experimental results were reported in terms of bandwidth, center frequency, and phase difference between $S_{21}$ and $S_{31}$. We confirm that our design will be useful in the future microwave power systum.

Design of Multivalued Logic Circuits using Current Mode CMOS (전류모드 CMOS에 의한 다치논리회로의 설계)

  • Seong, Hyeon-Kyeong;Kang, Sung-Su;Kim, Heung-Soo
    • Proceedings of the KIEE Conference
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    • 1988.07a
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    • pp.278-281
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    • 1988
  • This paper realizes the multi-output truncated difference circuits using current mode CMOS, and presents the algorithm designing multi - valued logic functions of a given multivalued truth tables. This algorithm divides the discrete valued functions and the interval functions, and transforms them into the truncated difference functions. The transformed functions are realized by current mode CMOS. The technique presented here is applied to MOD4 addition circuit and GF(4) multiplication circuit.

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A Weighted Random Pattern Testing Technique for Path Delay Fault Detection in Combinational Logic Circuits (조합 논리 회로의 경로 지연 고장 검출을 위한 가중화 임의 패턴 테스트 기법)

  • 허용민;임인칠
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.12
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    • pp.229-240
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    • 1995
  • This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

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Analysis of the Gravity Effect on the Distribution of Refrigerant Flow in a Multi-circuit Condenser (다분지 응축기의 냉매유량 분배에 미치는 중력의 영향을 고려한 해석방법)

  • Lee Jangho;Kim Moo Hwan
    • Korean Journal of Air-Conditioning and Refrigeration Engineering
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    • v.16 no.12
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    • pp.1167-1174
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    • 2004
  • The method to consider gravity effect on the performance of a condenser is developed, and a simple condenser having 'nU' type two circuits is analyzed. Each circuit has the same length and inlet air-side operational conditions. The only difference between two circuits is the direction of refrigerant flow, which is exactly opposite each other between the upper 'n' type circuit and the lower 'U' type circuit. It is shown that the gravity makes the distribution of refrigerant flow uneven in the two circuits at lower refrigerant flow rates; heat transfer rate also becomes uneven. Moreover, much of the refrigerant exists as liquid state in the circuit having low refrigerant flow rate, which will make the cycle balance unstable in the refrigeration cycle system like a heat pump.

Implementation of Quadrifilar Helical Antenna Using Phase Difference with PCB Feeding Line (PCB 피딩 라인에 의한 위상차를 이용한 Quadrifilar Helical Antenna의 제작)

  • Park, Sang-Jo
    • Journal of the Korea Society of Computer and Information
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    • v.13 no.6
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    • pp.211-216
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    • 2008
  • Gap fillar antennas are needed for serving the high quality of DMB through the cellular phone by eliminating the shadow regions among buildings or underground. We implement Quadrifilar Helical Antenna using phase difference with PCB feeding lines without coaxial cables and four impedance matching circuits. It is shown that the antenna characteristics is affected by the size and diameter through the simulation process using MicroWave Studio and it is applied for implementing QHA. Experiment results confirm that the performance can be gained as same as the simulation data by using the phase difference with PCB feeding lines without additional impedance matching circuits.

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Inhibitotory Synapses of Single-layer Feedback Neural Network (궤환성을 갖는 단츰신경회로망의 Inhibitory Synapses)

  • Kang, Min-Je
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.49 no.11
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    • pp.617-624
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    • 2000
  • The negative weight can be ofter seen in Hopfield neural network, which is difficult to implement negative conductance in circuits. Usually, the inverted output of amplifier is used to avoid negative resistors for expressing the negative weights in hardware implementation. However, there is some difference between using negative resistor and the inverted output of amplifier for representing the negative weight. This difference is discussed in this paper.

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Etchless Fabrication of Cu Circuits Using Wettability Modification and Electroless Plating (젖음성 차이와 무전해도금을 이용한 연성 구리 회로패턴 형성)

  • Park, Sang-Jin;Ko, Tae-Jun;Yoon, Juil;Moon, Myoung-Woon;Han, Jun Hyun
    • Korean Journal of Materials Research
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    • v.25 no.11
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    • pp.622-629
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    • 2015
  • Cu circuits were successfully fabricated on flexible PET(polyethylene terephthalate) substrates using wettability difference and electroless plating without an etching process. The wettability of Cu plating solution on PET was controlled by oxygen plasma treatment and $SiO_x$-DLC(silicon oxide containing diamond like carbon) coating by HMDSO(hexamethyldisiloxane) plasma. With an increase of the height of the nanostructures on the PET surface with the oxygen plasma treatment time, the wettability difference between the hydrophilicity and hydrophobicity increased, which allowed the etchless formation of a Cu pattern with high peel strength by selective Cu plating. When the height of the nanostructure was more than 1400 nm (60 min oxygen plasma treatment), the reduction of the critical impalement pressure with the decreasing density of the nanostructure caused the precipitation of copper in the hydrophobic region.

Estimation of Fault Location on Transmission Lines using Current Phasor (전류 페이저를 이용한 송전선로 고장점 추정 알고리즘)

  • Yeo, Sang-Min;Kim, Chul-Hwan
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.11
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    • pp.2095-2100
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    • 2009
  • Since most of the Extra High Voltage (EHV) transmission lines are untransposed and multi-circuits, errors are occurred inevitably because of the unbalanced impedances of the lines and so on. Therefore, a distance relaying algorithm applicable to the untransposed multi-circuits transmission lines needs to be developed. The proposed algorithm of fault location estimation in the paper uses the fundamental phasor to reduce the effects of the harmonics. This algorithm also analyzes the second-order difference of the phasor to calculate the traveling times of waves generated by faults. The traveling time of the waves generated by faults is derived from the second-order difference of the phasor. Finally, the distance from the relaying point to the faults is estimated using the traveling times. To analyze the performance of the algorithm, a power system with the EHV untransposed double-circuit transmission lines are modeled and simulated under various fault conditions such as several fault types, fault locations, fault inception angles and fault resistances. The results of the simulations show that the proposed algorithm has the capability to estimate the fault locations quickly and accurately.

A Case Study of Online Practice Activities in Non-face-to-face Class - 'Introduction to Electric Circuits and Lab' Course (비대면 수업에서 온라인 실습활동의 사례- '기초전기회로 및 실습' 교과목을 중심으로)

  • Han, Anna;Lee, Ho-Cheol
    • Journal of Engineering Education Research
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    • v.25 no.1
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    • pp.22-32
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    • 2022
  • The purpose of this study is to design and operate non-face-to-face online practice class in engineering education, and to explore students' perceptions and effectiveness of them. To this end, after developing and implementing a strategy for non-face-to-face online practice activities in the 'Introduction to Electric Circuits and Lab' course, the questionnaire responses of 47 learners were analyzed, and the group differences were investigated using Kruskal-Wallis test. As a result, it was found that students' perceptions of non-face-to-face online practice class were positive in terms of learning effect, learning convenience, interaction, and satisfaction. The group difference according to the face-to-face/non-face-to-face preference method was found to be higher in the group that preferred non-face-to-face class in terms of learning convenience, interaction and satisfaction. As for the group difference according to the number of questions and answers of the learners, the group who answered the question showed a higher awareness of the learning convenience and interaction than the group that did not. In addition, implications for designing a learning environment for non-face-to-face online practice classes were presented.