• 한국결정학회지
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• 제16권2호
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• pp.141-148
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• 2005

It is well known that the general metals have a lot of grain boundaries. The grain boundaries play a negative role to increase the resistivity and to decrease the conductivity. The small resistivity and the large conductivity have been a goal of the material scientists, and no signal noise, perfect signal transfer, and the realization of the real sound are the dream of electronic engineers and audio manias. Generally, oxygen free copper (OFC) and Ohno continuous casting (OCC) copper cables have been used for the purpose of the precise signal transfer and low noise. However they still include a lot of grain boundaries. In our study, we have grown the single crystal by the Czochralski method and succeeded to produce single crystal wires from the crystal in the dimension of $0.5{\times}0.5{\times}2500mm$. The produced wire still possesses very good single crystal properties. We observed the structure of the wire, and measured the resistance and impedance. Glow Discharge Spectrometer (GDS) was used for analyzing the compositions of copper single crystals and commercial copper. Current-Voltage curve, resistance, total harmonic distortion and speaker frequency response were measured for comparing electrical and acoustic properties of two samples.

• 조명전기설비학회논문지
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• 제22권4호
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• pp.54-60
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• 2008

2002년부터 시행되어오고 있는 제조물 책임법에 의해 사고케이블의 원인분석과 사고패턴에 대한 데이터베이스화가 중요하다. 더욱이 가속열화상태에서 전력케이블 사고의 패턴 및 모의실험은 데이터베이스 시스템 구축에 필요하다. 본 논문에서는 열 열화 따른 22.9[kV]이하 케이블의 열 충격시험을 수행하였다. 이 시험은 IEC60811-3-1에 따른다. 시험결과로부터, 22.9[kV]급 A사 전력케이블은 표면이 변색되었고 길이방향으로 급격하게 감소되었다. 특히, A사 전력케이블의 열 중량 특성이 심하게 변함에 따라, 케이블 제조상의 문제일 것이라 추측된다. 만약 전력케이블의 제조상의 결함에 의한 것이라면, 피해자들은 PL환경 하에 손해배상을 받을 수 있을 것이다.

• 전기학회논문지
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• 제66권5호
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• pp.800-805
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• 2017

The accelerated thermal ageing of CSPE (chlorosulfonated polyethylene) was carried out for 16.82, 50.45, and 84.09 days at $110^{\circ}C$, equivalent to 20, 60, and 100 years of ageing at $50^{\circ}C$ in nuclear power plants, respectively. As the accelerated thermally aged years increase, the insulation resistance and resistivity of the CSPE decrease, and the capacitance, relative permittivity and dissipation factor of those increase at the measured frequency, respectively. As the accelerated thermally aged years and the measured frequency increase, the phase degree of response voltage vs excitation voltage of the CSPE increase but the phase degree of response current vs excitation voltage decrease, respectively. As the accelerated thermally aged years increase, the apparent density, glass transition temperature and the melting temperature of the CSPE increase but the percent elongation and % crystallinity decrease, respectively. The differential temperatures of those are $0.013-0.037^{\circ}C$ and, $0.034-0.061^{\circ}C$ after the AC and DC voltages are applied to CSPE-0y and CSPE-20y, respectively; the differential temperatures of those are $0.011-0.038^{\circ}C$ and $0.002-0.028^{\circ}C$ after the AC and DC voltages are applied to CSPE-60y and CSPE-100y, respectively. The variations in temperature for the AC voltage are higher than those for the DC voltage when an AC voltage is applied to CSPE. It is found that the dielectric loss owing to the dissipation factor($tan{\delta}$) is related to the electric dipole conduction current. It is ascertained that the ionic (electron or hole) leakage current is increased by the partial separation of the branch chain of CSPE polymer as a result of thermal stress due to accelerated thermal ageing.

• Progress in Superconductivity
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• 제8권2호
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• pp.143-151
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• 2007

Accurate measurements of the microwave surface resistance (Rs) of high temperature superconductor (HTS) films are important with regard to applications of HTS materials for wireless communications. As the surface resistance values of HTS films are usually extracted from the measured unloaded quality factor ($Q_0$) of resonators made of HTS films, it is essential to measure the resonator $Q_0$ with accuracy. The $TE_{011}\;mode\;Q_0$ of sapphire resonators with the endplates made of $YBa_2Cu_3O_{7-{\delta}}$(YBCO) film on $LaAlO_3$ is measured by using the S-parameter circle-fit method at a frequency of about 19.6 GHz and temperatures of 30 K to 90 K, which is compared with the measured values by using the Lorentzian-fit method. Good agreements are found between the two sets of $Q_0$ values measured by using the two different methods whether the resonator is used in a weak-coupling scheme or a strong-coupling scheme, showing reliability of both methods fur measuring the resonator $Q_0$ accurately. The $Q_0$ of sapphire resonators with a gap between the top plate and the rest of the resonator is also discussed.

• 한국초전도ㆍ저온공학회논문지
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• 제16권4호
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• pp.66-70
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• 2014

The superconducting fault current limiter (SFCL) is an electrical power system device that detects the fault current automatically and limits the magnitude of the current below a certain safety level. The SFCL module does not have any electrical resistance below the critical temperature, which facilitates lossless power transmission in the electric power system. Once given the fault current, however, the superconducting conductor exhibits extremely high electrical resistance, and the magnitude of the current is accordingly limited to a low value. Therefore, SFCL should be maintained at a temperature below the critical temperature, which justifies the cryogenic cooling system as a mandatory component. This report is a study which reported on the cooling system for the 154 kV-class hybrid SFCL owned by Korea Electric Power Corporation (KEPCO). Using the cryocooler, the temperature of liquid nitrogen (LN2) was lowered to 71 K. The cryostat was pressurized to 5 bars to improve the dielectric strength of nitrogen and suppress nitrogen bubble foaming during operation of SFCL. The SFCL module was immersed in the liquid nitrogen of the cryostat to maintain the superconducting state. The performance test results of the key components such as cryocooler, LN2 circulation pump, cold box, and pressure builder are shown in this paper.

• 세라미스트
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• 제21권2호
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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• pp.35-43
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• 2001

Flip chip assembly on organic substrates using ACAs have received much attentions due to many advantages such as easier processing, good electrical performance, lower cost, and low temperature processing compatible with organic substrates. ACAs are generally composed of epoxy polymer resin and small amount of conductive fillers (less than 10 wt.%). As a result, ACAs have almost the same CTE values as an epoxy material itself which are higher than conventional underfill materials which contains lots of fillers. Therefore, it is necessary to lower the CTE value of ACAs to obtain more reliable flip chip assembly on organic substrates using ACAs. To modify the ACA composite materials with some amount of conductive fillers, non-conductive fillers were incorporated into ACAs. In this paper, we investigated the effect of fillers on the thermo-mechanical properties of modified ACA composite materials and the reliability of flip chip assembly on organic substrates using modified ACA composite materials. Contact resistance changes were measured during reliability tests such as thermal cycling, high humidity and temperature, and high temperature at dry condition. It was observed that reliability results were significantly affected by CTEs of ACA materials especially at the thermal cycling test. Results showed that flip chip assembly using modified ACA composites with lower CTEs and higher modulus by loading non-conducting fillers exhibited better contact resistance behavior than conventional ACAs without non-conducting fillers. Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of $SiO_2filler$ to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. Our results indicate that the electrical performance of ACF combined with electroless Wi/Au bump interconnection is comparable to that of solder joint.

• 한국정보통신학회논문지
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• 제7권8호
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• pp.1591-1597
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• 2003

본 논문에서는 HEMT(Agilent ATF­34143)를 이용한 부성저항 특성을 갖는 능동 인덕터와 캐패시터를 이용해 능동 공진 발진기 제작에 응용하였다. 5.5GHz 대역에서 능동 인덕터는 ­25$\Omega$의 부성저항과 2.4nH의 인덕턴스를 갖고, 능동 캐패시터는 ­14$\Omega$의 부성저항과 0.35pF의 캐패시턴스를 갖도록 설계하였다. 설계된 능동 인덕터와 캐패시터를 이용 5.8GHz ISM 대역의 국부 발진기로 사용 가능한 능동 공진 발진기를 설계하였다. 애질런트사의 ADS 2002C를 이용 시뮬레이션 하였다. 설계된 발진기는 유전율 3.38, 유전체 두께 0.508mm, 금속 두께 0.018mm인 기판위에 HMIC 형태로 구현하였다. 제작된 능동 공진 발진기는 5.68GHz의 기본 발진주파수에서 ­3.6㏈m의 출력을 얻었고, 100KHz 옵셋에서 ­81㏈c1/Hz의 위상잡음 특성을 갖는다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.3-4
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• 2006

In this paper, a nickel silicide technology with post-silicidation annealing effect for thin film SOI devices is investigated in detail. Although lower resistivity Ni silicide can be easily obtained at low forming temperature, poor thermal stability and changing of characteristic are serious problems during the post silicidation annealing like ILD (Inter Layer Dielectric) deposition or metallization. So these effects are observed as deposited Ni thickness differently on As doped SOI (Si film 30nm). Especially, the sheet resistance of Ni thickness deposited 20nm was lower than 30nm before the post silicidation annealing. But after the post silicidation annealing, the sheet resistance was changed. Therefore, in thin film SOI MOSFETs or Ni-FUSI technology that the Si film is less than 50nm, it is important to decide the thickness of deposited Ni in order to avoid forming high resistivity silicide.

• 전기전자학회논문지
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• 제22권1호
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• pp.180-184
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• 2018

산화갈륨 ($Ga_2O_3$)과 탄화규소 (SiC)는 넓은 밴드 갭 ($Ga_2O_3-4.8{\sim}4.9eV$, SiC-3.3 eV)과 높은 임계전압을 갖는 물질로서 높은 항복 전압을 허용한다. 수직 DMOSFET 수평구조에 비해 높은 항복전압 특성을 갖기 때문에 고전압 전력소자에 많이 적용되는 구조이다. 본 연구에서는 2차원 소자 시뮬레이션 (2D-Simulation)을 사용하여 $Ga_2O_3$와 4H-SiC 수직 DMOSFET의 구조를 설계하였으며, 항복전압과 저항이 갖는 trade-off에 관한 파라미터를 분석하여 최적화 설계하였다. 그 결과, 제안된 4H-SiC와 $Ga_2O_3$ 수직 DMOSFET구조는 각각 ~1380 V 및 ~1420 V의 항복 전압을 가지며, 낮은 게이트 전압에서의 $Ga_2O_3-DMOSFET$이 보다 낮은 온-저항을 갖고 있지만, 게이트 전압이 높으면 4H-SiC-DMOSFET가 보다 낮은 온-저항을 갖을 수 있음을 확인하였다. 따라서 적절한 구조와 gate 전압 rating에 따라 소자 구조 및 gate dielectric등에 대한 심화 연구가 요구될 것으로 판단된다.