• Transactions on Electrical and Electronic Materials
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• 제13권1호
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• pp.31-34
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• 2012

The addition of nano/micro silica into unsaturated polyester resin (UPR) results in the improvement of the electrical properties of Silica-UPR composites. The surface, volume resistivity, dielectric strength, dissipation factor and dry arc resistivity of nano silica-UPR composites were found to improve significantly. The effects of the nano and micro fillers in UPR have been evaluated. They are presented in this paper. To evaluate the electrical properties of the nano & micro composites, all the measurements were done as per the prescribed methods in ASTM. It was observed that the addition of nano silica improves the electrical properties as compared to micro silica. The better dispersion of silica particles in unsaturated polyester resin enhances the electrical properties of silica-UPR composites.

• 한국전기전자재료학회논문지
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• 제22권6호
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• pp.466-468
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• 2009

The metal-insulator-silicon (MIS) capacitors with $SiO_2$ and high-k dielectrics ($HfO_2$, $Al_2O_3$) were fabricated, and the current-voltage characteristics were investigated. Especially, an effective barrier height between metal gate and dielectric was extracted by using Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot of quantum mechanical(QM) modeling. The calculated barrier heights of thermal $SiO_2$, ALD $SiO_2$, $HfO_2$ and $Al_2O_3$ are 3.35 eV, 0.6 eV, 1.75 eV, and 2.65 eV, respectively. Therefore, the performance of non-volatile memory devices can be improved by using engineered tunnel barrier which is considered effective barrier height of high-k materials.

• 한국정밀공학회지
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• 제18권12호
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• pp.192-199
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• 2001

Chemical mechanical planarization (CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There hale been serious problems in CMP in terms of repeatability and deflects in patterned wafers. Especial1y, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasives and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using CeO$_2$is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method fur developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• 한국레이저가공학회지
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• 제14권4호
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• pp.14-20
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• 2011

The advantage of using lasers for through silicon via (TSV) drilling is that they allow higher flexibility during manufacturing because vacuums, lithography, and masks are not required; furthermore, the lasers can be applied to metal and dielectric layers other than silicon. However, conventional nanosecond lasers have disadvantages including that they can cause heat affection around the target area. In contrast, the use of a picosecond laser enables the precise generation of TSVs with a smaller heat affected zone. In this study, a comparison of the thermal and crystallographic defect around laser-drilled holes when using a picosecond laser beam with varing a fluence and repetition rate was conducted. Notably, the higher fluence and repetition rate picosecond laser process increased the experimentally recast layer, surface debris, and dislocation around the hole better than the high fluence and repetition rate. These findings suggest that even the picosecond laser has a heat accumulation effect under high fluence and short pulse interval conditions. To eliminate these defects under the high speed process, the CDE (chemical downstream etching) process was employed and it can prove the possibility to applicate to the TSV industry.

• 한국표면공학회지
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• 제32권3호
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• pp.447-451
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• 1999

Silver has the highest electrical conductivity of all metals and consequently this property is an attractive feature which makes it a leading candidate for use in electronic devices. The research conducted was focused primarily on the development of a process for obtaining a deposited silver-coating onto alumina, for applications related to electrical-conducting devices and, ancillarily, catalysts. Alumina balls and plane substrates were utilized for the investigation. The coating process employed an aqueous ammoniacal silver-nitrate electrolytes with a formaldehyde solution as the reductant. Modifying additives-an activator which would be expected to promote good deposition-characteristics onto the (dielectric) substrate and an inhibitor which would obviate homogeneous reduction (precipitation) of silver was observed when the activator-containing silver-electrolyte reductant constituents were combined. However, the silver-electrolyte/reductant system with inhibitor could be employed (at 8$0^{\circ}C$) to achieve a viable (subject to future research optimization) coating on alumina. The influence of the processing temperature on the deposition process was delineated during the course of the research. The morphology of the deposited-silver on the alumina balls was assessed by SEM imaging. A tape-peel test was employed, with the plane substrates, to semi-quantitatively characterize the adhesion to the alumina.

• Journal of Magnetics
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• 제12권1호
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• pp.21-26
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• 2007

Si-based electromagnetic noise suppressors on coplanar waveguide transmission lines incorporated with a $SiO_2$ dielectric layer and a nanogranular Co-Fe-Al-O magnetic thin film are reported. Unlike glass-based devices, large signal attenuation is observed even in the bare structure without coating the magnetic thin film. Much larger signal attenuation is achieved in fully integrated devices. The transmission scattering parameter ($S_{21}$) is as small as -90 dB at 20 GHz at the following device dimensions; the thicknesses of the $SiO_2$ and Co-Fe-Al-O thin films are 0.1 $\mu$m and 1 $\mu$m, respectively, the length of the transmission line is 15 mm, and the width of the magnetic thin film is 2000 $\mu$m. In all cases, the reflection scattering parameter ($S_{11}$) is below -10 dB over the whole frequency band. Additional distributed capacitance formed by the Cu transmission line/$SiO_2$/Si substrate is responsible for these characteristics. It is considered that the present noise suppressors based on the Si substrate are a first important step to the realization of MMIC noise suppressors.

• 전기전자학회논문지
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• 제23권2호
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• pp.614-621
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• 2019

본 논문은 integral equation-fast Fourier transform(IE-FFT)과 block matrix preconditioner(BMP)를 이용하여 침투 가능한 구조물의 전자기 산란 문제를 다룬다. IE-FFT는 모멘트 법(the method of Moments : MoM)에 의해 형성된 행렬방정식의 해를 계산하기 위하여 반복법의 연산량을 상당히 개선할 수 있다. 또한 전기적으로 커다란 구조물로부터 형성된 행렬방정식에 BMP가 적용된 반복법을 적용하면 반복 횟수를 크게 줄여 행렬방정식의 해를 빠르게 계산할 수 있다. 수치해석 결과는 IE-FFT와 BMP를 적용하여 침투 가능한 구조물의 전자기 산란 문제를 빠르고 정확하게 계산할 수 있음을 보여준다.

• Composites Research
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• 제32권5호
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• pp.211-215
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• 2019

정적인 상태인 체외 환경(in vitro)에서의 세포배양 과정은 실제 생체 내 환경에서의 세포발달과정과는 많은 차이가 존재한다. 따라서, 체내 환경의 정밀한 모사를 위해서는, 기계적인 자극을 세포에 전달하여 줄 수 있는 동적 세포배양장치가 필수적이다. 하지만 기존의 동적 세포배양장치에는 튜브, 펌프, 모터 등의 비교적 복잡한 장치들을 필요로 하였으며, 전달되는 기계적 자극도 단순한 형태였다. 본 연구에서는 단순한 장치로 구동되는 동적 세포배양장치를 위하여 전기활성고분자(EAP) 구동기를 동력원으로 하는 소형 동적 세포배양장치를 설계하였다. 이 장치는 다양한 기계적 자극을 세포에 전달하는 것이 가능하다.

• 한국전기전자재료학회논문지
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• 제35권3호
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• pp.246-254
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• 2022

Localized heat can be generated using electrically conductive word-lines built into a 3D NAND flash memory string. The heat anneals the gate dielectric layer and improves the endurance and retention characteristics of memory cells. However, even though the electro-thermal annealing can improve the memory operation, studies to investigate material failures resulting from electro-thermal stress have not been reported yet. In this context, this paper investigated how applying electro-thermal annealing of 3D NAND affected mechanical stability. Hot-spots, which are expected to be mechanically damaged during the electro-thermal annealing, can be determined based on understanding material characteristics such as thermal expansion, thermal conductivity, and electrical conductivity. Finally, several guidelines for improving mechanical stability are provided in terms of bias configuration as well as alternative materials.

• 한국전기전자재료학회논문지
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• 제35권6호
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• pp.576-580
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• 2022

Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.