• Journal of the Korean Wood Science and Technology
• /
• 제39권2호
• /
• pp.125-131
• /
• 2011

The characteristics of radio-frequency/vacuum drying Japanese larch boxed heart round logs with 150 mm and 210 mm in diameter and 2,500 mm in length, subjected to compressive loading, after the pretreatment of kerf were investigated. The results of this study were as the follows: The drying time of about 120 hours~130 hours was needed from green to about 15 percent of moisture content. The gradient of final moisture content for all specimens was very gentle in both longitudinal and transverse directions owing to dielectric heating. The surface checks seriously occurred although the occurrence extent of surface check for the kerfed specimens was slight compared with that for the control specimens because drying stress was relieved by kerf. The occurrence of surface checks for the L-specimen was more serious than that for the S-specimen.

• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
• /
• pp.53-58
• /
• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
• /
• pp.370-373
• /
• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 하계학술대회 논문집 C
• /
• pp.1646-1648
• /
• 2000

This paper investigated structural and electrical properties of $Y_{2}O_3$ as a buffer layer of sin91r transistor FRAM (ferroelectric RAM). $Y_{2}O_3$ buffer layers were deposited at a low substrate temperature below 400$^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post- annealing temperature, and suppression of interfacial $SiO_2$ layer generation. for a well-fabricated sample, we achieved that leakage current density ($J_{leak}$) in the order of $10^{-7}A/cm2$, breakdown electric field ($E_{br}$) about 2 MV/cm for $Y_{2}O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_{2}O_3$/Si as low as $8.72{\times}10^{10}cm^{-2}eV^{-1}$. The low interface states were obtained from very low lattice mismatch less than 1.75%.

• 한국재료학회지
• /
• 제17권5호
• /
• pp.263-267
• /
• 2007

Hafnium oxide $(HfO_2)$ films were deposited on Si(100) substrates by remote plasma-enhanced atomic layer deposition (PEALD) method at $250^{\circ}C$ using TEMAH [tetrakis(ethylmethylamino)hafnium] and $O_2$ plasma. $(HfO_2)$ films showed a relatively low carbon contamination of about 3 at %. As-deposited and annealed $(HfO_2)$ films showed amorphous and randomly oriented polycrystalline structure. respectively. The interfacial layer of $(HfO_2)$ films deposited using remote PEALD was Hf silicate and its thickness increased with increasing annealing temperature. The hysteresis of $(HfO_2)$ films became lower and the flat band voltages shifted towards the positive direction after annealing. Post-annealing process significantly changed the physical, chemical, and electrical properties of $(HfO_2)$ films. $(HfO_2)$ films deposited by remote PEALD using TEMAH and $O_2$ plasma showed generally improved film qualities compare to those of the films deposited by conventional ALD.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 하계학술대회 논문집
• /
• pp.47-50
• /
• 2000

This paper investigated structural and electrical properties of $Y_2$ $O_3$ as a buffer layer of single transistor FRAM (ferroelectric RAM). $Y_2$ $O_3$ buffer layers were deposited at a low substrate temperature below 40$0^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post-annealing temperature, and suppression of interfacial $SiO_2$ layer generation. For a well-fabricated sample, we achieved that leakage current density ( $J_{leak}$) in the order of 10$^{-7}$ A/$\textrm{cm}^2$, breakdown electric field ( $E_{br}$ ) about 2 MV/cm for $Y_2$ $O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_2$ $O_3$/Si as low as 8.72x1010 c $m^{-2}$ e $V^{-1}$ . The low interface states were obtained from very low lattice mismatch less than 1.75%.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
• /
• pp.20-23
• /
• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• 한국식품저장유통학회지
• /
• 제24권7호
• /
• pp.908-914
• /
• 2017

국내에서 생산되는 벼의 저장안전성 확보를 위한 기초기반연구로 플라즈마 기술을 이용하여 벼의 저장기간 및 온도에 따른 미생물 생육 및 성분 변화를 관찰하였다. 플라즈마 시스템은 컨테이너형 유전격벽 플라즈마로 공기방전방식을 이용하여 삼광, 청품, 미소미, 팔방미 품종을 0, 10 및 20분간 처리하여 $4^{\circ}C$, $25^{\circ}C$에서 2달간 저장하여 실험하였다. 미생물 생육 변화를 관찰한 결과 저장 초기에는 일반호 기성 미생물은 3.46-3.86 log CFU/g, 곰팡이는 2.27-2.86 log CFU/g이 검출되었다. 저장온도 및 기간에 따라 일반호기성 미생물 및 곰팡이의 생육은 증가하였으며, 품종간의 큰 차이는 없었다. 저장한 후의 미생물 분석 결과 플라즈마 처리군의 미생물이 약 1.50 log CFU/g 적게 생육되었다. 플라즈마 처리한 벼의 수분함량을 측정한 결과 플라즈마 처리에 의한 큰 차이는 관찰되지 않았으나, 저장온도가 올라가면 수분함량이 감소하는 것을 확인하였다. 지방은 플라즈마에 의해 감소하는 경향을 보였으나, 단백질 함량은 플라즈마 및 저장조건에 따른 일관적인 변화는 관찰되지 않았다. 아밀로스 함량의 경우 삼광, 청품, 미소미 품종은 플라즈마에 의한 함량 변화는 관찰되지 않았으나 팔방미는 증가하는 경향을 보였다. 이상의 결과를 종합하여 볼 때 플라즈마에 의해 벼의 저장안전성을 개선할 수 있으며 품질 변화의 최소화를 위하여 저온저장이 효과적이라고 판단된다.

• 한국식품위생안전성학회지
• /
• 제31권5호
• /
• pp.375-379
• /
• 2016

국내 시판 중인 선식의 유통 안전성 확보를 위한 기초 기반연구로 대기압 플라즈마 처리한 선식의 품질 특성 평가를 진행하였다. 본 연구에서 이용한 플라즈마는 컨테이너형 유전격벽 플라즈마로 방전 가스는 공기를 활용하여 0, 5, 10 및 20분 처리하였고 미생물 감균효과, 색도, pH 관능평가를 진행하였다. 일반 호기성 미생물 분석 결과 20분 처리 시 약 1.70 log CFU/g 감소하였으며 B. cereus, B. subtilis 및 E. coli O157:H7을 이용한 접종 시험 결과 각각 2.20, 2.22 및 2.50 log CFU/g 감소하였다. 색도 측정결과 플라즈마 처리에 의해 명도 값은 증가하였으나 적색도 및 황색도는 감소하였다. 플라즈마 처리에 의한 선식의 pH 측정 결과 처리시간에 따라 감소하는 경향을 보였다. 하지만 플라즈마 처리에 의해 단백질 지질산화가 일어나 관능 품질이 저하되는 경향을 보였다. 따라서 공기로 방전된 대기압 플라즈마 기술은 선식의 품질안전성을 개선할 수 있으나, 관능적 품질 특성 개선을 위한 후속연구가 필요하다고 판단된다.

• 한국광학회지
• /
• 제13권3호
• /
• pp.215-222
• /
• 2002

광기록매체용 Ge-Sb-Te다층박막 성장과정을 in-situ 타원계를 사용하여 실시간으로 모니터하여 각 층의 두께를 제어하고 성장된 Ge-Sb-Te 다층박막을 ex-site 분광타원법으로 확인하였다. 보호층인 ZnS-SiO$_2$와 기록층인 Ge$_2$Sb$_2$Te$_{5}$을 단결정실리콘 기층 위에 스퍼터링 방법으로 각각 성장시키면서 구한 타원상수 성장곡선을 분석하여 성장에 따르는 보호층의 균일성 및 기록 층의 밀도변화를 파악하고 이를 기초로 하여 Ge-Sb-Te광기록 다층박막의 두께를 정밀하게 제어하였다. Ge$_2$Sb$_2$Te$_{5}$ 단층박막 시료의 복소굴절율은 eX-Situ 분광타원분석을 통하여 구하였다. 제작된 다층구조는 설정된 다층구조인 ZnS-SiO$_2$(1400$\AA$)$\mid$ GST(200 $\AA$)$\mid$ZnS-SiO$_2$(200$\AA$)와 각 층의 두께 및 전체 두께에서 1.5% 이내에서 일치하는 정확도를 보여주었다.주었다.