• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.252.1-252.1
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• 2013

Hexagonal boron nitride (h-BN) is a two dimensional material which has high band-gap, flatness and inert properties. This properties are used various applications such as dielectric for electronic device, protective coating and ultra violet emitter so on. 1) In this report, we were growing h-BN sheet directly on sapphire 2"wafer. Ammonia borane (H3BNH3) and nickel were deposited on sapphire wafer by evaporate method. We used nickel film as a sub catalyst to make h-BN sheet growth. 2) During annealing process, ammonia borane moved to sapphire surface through the nickel grain boundary. 3) Synthesized h-BN sheet was confirmed by raman spectroscopy (FWHM: ~30cm-1) and layered structure was defined by cross TEM (~10 layer). Also we controlled number of layer by using of different nickel and ammonia borane thickness. This nickel film supported h-BN growth method may propose fully and directly growing on sapphire. And using deposited ammonia borane and nickel films is scalable and controllable the thickness for h-BN layer number controlling.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.269-273
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• 2001

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. In this paper, we propose Stand Alone layout and In-Line layout are analyzed and compared while varying number of device variable changes. The comparison is performed through simulation using ProSys; a window 98 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, In-Line layout is more efficient in terms of production quantity. However, as the number of device variable change is more than 14 titles, Stand Alone layout prevails over In-Line layout.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2009.04a
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• pp.76-77
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• 2009

This paper is concerned with the development of the piezoelectric energy harvesting(PEH) device using Wind. In this study, the piezoelectric energy harvesting system consisting of a cantilever with a pinwheel and piezoelectric wafer was investigated in detail both theoretically and experimentally. The power output characteristics of the PEH was then calculated and discussed. Theoretical and experimental results showed that the PEH was able to charge a battery with ambient vibrations but still needed an effective mechanism which can convert mechanical energy to electrical energy and an optimal electric circuit which dissipates small energy.

• ETRI Journal
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• v.17 no.4
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.22-23
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• 2006

Proton irradiation technology was used for improvement of switching characteristics of the PT-IGBT. Proton irradiation was carried out at 5.56 MeV energy with $1{\times}10^{12}/cm^2$ doze from the back side of the wafer. Characterization of the device was performed by I-V, breakdown voltage, threshold voltage, and turn-off delay time measurement. For irradiated device by 5.56 MeV energy, the breakdown voltage and the threshold voltage were 730 V and 6.5~6.6 V, respectively. The turn-off time has been reduced to 170 ns, which was original $6\;{\mu}s$ for the un-irradiated device.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.82-86
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• 2021

In this study, we investigated the oxygen partial pressure effect of ITO films for electrodes of oxide-based Thin-Film Transistor (TFT). Firstly, we deposited single ITO films on the glass substrate at room temperature. ITO films were prepared at the various partial pressures of oxygen gas 0-7.4% (O₂/(Ar+O₂)). As increasing oxygen on the process of film deposition, electrical properties were improved and optical transmittance increased in the visible light range (300-800 nm). For the electrode of TFT, we fabricated a TFT device (W/L=1000/200 ㎛) with ITO films as the source and drain electrode on the silicon wafer. Except for the TFT device combined with ITO film prepared at the oxygen partial pressure ratio of 7.4%, We confirmed that TFT devices with ITO films via FTS system operated as a driving device at threshold voltage (V_th) of 4V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.440-440
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• 2009

Semiconductor nanowires offer exciting possibilities as components of solar cells and have already found applications as active elements in organic, dye-sensitized, quantum-dot sensitized, liquid-junction, and inorganic solid-state devices. Among many semiconductors, silicon is by far the dominant material used for worldwide photovoltaic energy conversion and solar cell manufacture. For silicon wire to be used for solar device, well aligned wire arrays need to be fabricated vertically or horizontally. Macroscopic silicon wire arrays suitable for photovoltaic applications have been commonly grown by the vapor-liquid-solid (VLS) process using metal catalysts such as Au, Ni, Pt, Cu. In the case, the impurity issues inside wire originated from metal catalyst are inevitable, leading to lowering the efficiency of solar cell. To escape from the problem, the wires of purity of wafer are the best for high efficiency of photovoltaic device. The fabrication of wire arrays by the electrochemical etching of silicon wafer with photolithography can solve the contamination of metal catalyst. In this presentation, we introduce silicon wire arrays by electrochemical etching method and then fabrication methods of radial p-n junction wire array solar cell and the various merits compared with conventional silicon solar cells.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.647-650
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• 2006

Low temperature polycrystalline silicon (LTPS) technology using a high power laser have been widely applied to thin film transistors (TFTs) for liquid crystal, organic light emitting diode (OLED) display, driver circuit for system on glass (SOG) and static random access memory (SRAM). Recently, the semiconductor industry is continuing its quest to create even more powerful CPU and memory chips. This requires increasing of individual device speed through the continual reduction of the minimum size of device features and increasing of device density on the chip. Moreover, the flat panel display industry also need to be brighter, with richer more vivid color, wider viewing angle, have faster video capability and be more durable at lower cost. Kornic Systems Co., Ltd. developed the $KORONA^{TM}$ LTP/GLTP series - an innovative production tool for fabricating flat panel displays and semiconductor devices - to meet these growing market demands and advance the volume production capabilities of flat panel displays and semiconductor industry. The $KORONA^{TM}\;LTP/GLTP$ series using DPSS laser and XeCl excimer laser is designed for the new generation of the wafer & FPD glass annealing processing equipment combining advanced low temperature poly-silicon (LTPS) crystallization technology and object-oriented software architecture with a semistandard graphical user interface (GUI). These leading edge systems show the superior annealing ability to the conventional other method. The $KORONA^{TM}\;LTP/GLTP$ series provides technical and economical benefits of advanced annealing solution to semiconductor and FPD production performance with an exceptional level of productivity. High throughput, low cost of ownership and optimized system efficiency brings the highest yield and lowest cost per wafer/glass on the annealing market.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.72.2-72.2
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• 2010

Nowadays, the crystalline Si Solar cell are expected for economical renewable energy source. The cost of the crystalline Si solar cell are decreasing by improvement of its efficiency and decrease of the cost of the raw Si wafers for Solar cells. This Si wafer based crystalline Si solar cell is the verified technology from several decade of its history. Now, I will introduce one method that can be upgrade the efficiency by using simple and economical method. The name of this method is Rear Side Etching(RSE). The purpose of rear side etching is the elimination of n+ layer of rear side and increase of the flatness. The effects of rear side etching are the improvement of Voc and increase of efficiency by reducement series resistance and forming of uniform BSF. The experimental procedure for rear side etching is very simple. After anti-reflection coating on solar cell wafer, Solar cell wafer is etched by the etching chemical that react with only rear side not front side. This special chemical is no harmful to anti-reflection coating layer. It can only etched rear side of solar cell wafer. We can use etching image by optical microscope, minority carrier life time by WCT 120, SiNx thickness and refractive index by ellipsometer, cell efficiency for the RSE effect measurement. The key point of rear side etching is development of etching process condition that react with only rear side. If we can control this factor, we can achieve increase of solar cell efficiency very economically without new device.