• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.438-441
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• 2000

In this paper, Turbo rode is describing a performance near the Shannon's channel capacity limit. So, basic theory of turbo code and MAP,Log-MAP decoding algorithm was arranged. The foundation of this using VHDL, Log-MAP turbodecoder was implemented by Altera´s FLEX10K CPLD.

• Journal of information and communication convergence engineering
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• v.4 no.1
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• pp.1-4
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• 2006

Recently Web Services choreography working group of W3C has published the working draft on WSCDL (Web Services Choreography Description Language) version 1.0 which defines reusable common rules to govern the ordering of exchanged messages between Web Services participants. This paper considers a computing environment where mobile clients are interacting with Web Services providers based on a WSCDL specification. In order to effectively cope with the user and device mobility of such an environment, in this paper we present an ongoing work to develop a framework through which a mobile client can specify its preference on how conversation should take place. The proposed framework provides a flexible means for mobile clients to minimize the number of message exchanges while allowing them to adhere to the required choreography.

• Journal of Sensor Science and Technology
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• v.12 no.1
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• pp.44-50
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• 2003

A security system consisted of an infrared sensor and PLD(Programmable Logic Device) was fabricated to prevent an intruder. The fabricated system detect the intruder using infrared sensor and has password key pad to permit someone to enter the house and office. The control circuit of the system is designed by VHDL(Very high speed integrated Hardware Description Language). The system was demonstrated in various conditions and the output signals were displayed in LCD, LED, buzzer and so on. This designed system in this paper has a advantage to supplement additional function with ease.

• Journal of Power Electronics
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• v.16 no.2
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.556-559
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• 2011

최근 디지털 방송 서비스가 본격화가 이루어짐에 따라 디지털 콘텐츠는 기하급수적으로 늘어나고 있다. 또한 방송통신 융합 환경은 기존 셋탑 박스와 같은 방송 전용 단말기와 PC, 노트북, PDA와 같은 인터넷 단말기기, 그리고 모바일 폰과 같은 통신기기 사이의 벽을 허물고 있다. IPTV, SmartTV 시대의 도래로 방송통신 제공자의 양방향성 콘텐츠의 제공 및 상호연동 서비스의 제공은 중요한 이슈가 되었다. 이에 따라 다양한 단말기를 이용해 N-Screen이 가능하도록 방송통신 융합 서비스를 제공하고, 이를 위한 여러 콘텐츠 제작이 활발히 일어나고 있다. 이에 본 논문은 양방향성과 상호운용성을 높이기 위한 하나의 방법으로, 방송통신 융합서비스를 인터넷에 의한 전송과 방송 셋탑에 의한 전송에 있어서 상호 동일한 콘텐츠의 통일성을 유지하여 관리가 쉽도록 하는 Scalable Application Framework를 이용하였고 이를 실제 멀티미디어 모바일 단말기기에 적용하고 구현하였다. 이를 통해 앞으로 스마트 방송 시대에 대비할 수 있는 시스템의 대안을 제안하고자 한다. MPEG-21의 DID를 기초로 하여 SADL(Scalable Application Description Language)를 정의하고 이를 이용한 다양한 프레임워크 모델 중 일부인 멀티미디어 모바일 단말기기에 적용하여 이를 활용하는 방안에 대해 논의한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.237-241
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• 2005

In Bluetooth version 1.0, the frequency hopping algorithm was such that there was one piconet, using a specific frequency, resolving the frequency depending on the part of the digits of the device clock and the Bluetooth address. Basic pattern was a kind of a round-robin using 79 frequencies in the ISM band. At this point, a problem occurs if there were more than two devices using the same frequency within specific range. In this paper, we proposed a software-based adaptive frequency hopping method so that more than two wireless devices can stay connected without frequency crash. Suggested method was implemented with HDL(Hardware Description Language) and automatically synthesized and laid out. Implemented adaptive frequency hopping circuit operated well in 24MHz correctly.

• 전자공학회논문지 IE
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• v.45 no.4
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• pp.27-32
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• 2008

This paper presents the implementation of simple genetic algorithm using hardware description language for evolvable hardware embedded system. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results for several fitness functions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.2
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• pp.61-69
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• 2003

In this paper, we developed the U parameter test system which inspects the property of DC parameter for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC (Analogue to Digital Converter), DAC (Digital to Analogue Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. The CPLD part is designed by VHBL, which it generates the control and converts the serial data to parallel data. The proposed system has two test channels and it operates VFCS mode and CFVS mode. The range of test voltage is from 0[V] to 100[V], and the range of test current is from 0[mA] to 100[mA)]. The diode is tested. The test results have a good performance.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.202-205
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• 2012

최근 멀티미디어 분야에서 다양한 입/출력 장치들이 개발됨에 따라 입/출력 장치와 사용자 사이의 향상된 상호작용(AUI : Advanced User Interaction)을 위한 방법들이 연구되고 있다. AUI에서 정의되는 데이터는 입/출력 장치와 다양한 객체(비디오, 오디오, 2D 그래픽 객체, 애니메이션 등)로 표현되는 Scene Description 사이에서 서로 정보를 주고받기 위한 매체이다. 따라서 다양한 입/출력 장치와 사용자 사이의 향상된 상호작용을 위해서는 AUI 데이터 형식이 공통적으로 정의되어야한다. 이를 위해 ISO/IEC JTC1/SC29/WG11 Moving Picture Experts Group(MPEG)에서는 XML(Extensible Markup Language) 문서로 AUI 데이터 포맷을 표준화하기 위한 MPEG-U 프로젝트를 진행 중이다. 본 논문에서는 MPEG-U의 표준을 소개하고, 이의 타당성을 검증하기 위해서 MPEG-U 참조 소프트웨어를 설계하였다. MPEG-U 참조 소프트웨어는 크게 UID(User Interaction Device)의 데이터를 처리하는 사용자 인터페이스 입/출력부와 XML 문서를 처리하는 MPEG-U XML 생성/해석부로 구성된다. 사용자 인터페이스 입력부에서는 사용자의 손동작을 인식하여 AUI 파라미터로 저장하고, 이 파라미터를 MPEG-U XML 생성부에서 MPEG-U 표준 XML 스키마 구조로 서술하여 표준화된 AUI 데이터 포맷을 생성한다. 다시 표준화된 XML 문서를 읽어 MPEG-U XML 해석부에서 파라미터를 얻고, 사용자 인터페이스 출력부에서 GUI(Graphic User Interface)에서 그래픽 객체로 표현한다. 본 연구에서는 MPEG-U 참조 소프트웨어로 MPEG-U의 용용 예를 제시하고, 구현된 소프트웨어가 표준에 적합한지를 보였다.