• International Journal of Contents
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• v.7 no.1
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• pp.23-28
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• 2011

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

• KSBB Journal
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• v.23 no.1
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• pp.8-17
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• 2008

There are many different approaches to healing of acute and chronic ulcer and large skin defect, such as burn. Currently available wound covers fall into two categories. Permanent covering, such as autografts, and temporary ones, such as allograft including de-epidermized cadaver skin, bioartificial skin, xenografts, and synthetic dressings. Autologous skin grafting in the form of split- or full-thickness skin is still the good standard. Following on from developments in the 1980s involving the use of cultured keratinocyte grafts in wound healing, the last decade has been great progress in the fabrication of composite bioartificial skin grafts. However, two bottleneck on producing cultured bioartificial skin, whether of the simple epithelial cell sheet type, or the more complex composite type, continue to be the generation of sufficient keratinocytes cheaply and quickly and develop biocompatible dermal scaffolds. This article covers the development, clinical application, and current research directions associated with bioartificial skin.

• Proceedings of the CALSEC Conference
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• 1999.07a
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• pp.193-205
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• 1999

Nowadays, public domain software CALS/EC projects give their attention to the importance of test and evaluation (T＆E). This article proposed a survey on T＆E procedures of the international standards ISO 9000-3, ISO/IEC 9126 and ISO 14598, and of the U.S. Army pamphlet as well as that of MIL-STD-498. And features of testing tools such as their characteristics were reviewed for a reference in selecting appropriate one. Large-scale software projects often encounter with problems during T＆E, when they become close to the end of development cycle. The problems generally act as a bottleneck of a project, leading to slippage of the entire schedule. This article tried a close look at the problems and solution alternatives of the T＆E policy, management, and technical issues, and proposed a T＆E model to support a variety of software development environment.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.20 no.43
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• pp.163-174
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• 1997

Development of control model and system for AMS (Automated Manufacturing Systems) has long been interested by researchers. Presented in the paper is a systematic approach to constructing a Petri-nets(PNs) model of AMS and method for design a graphical model of a AMS by using a new modeling tool which is called PNs. So, the procedure of modeling in the AMS is the same as current practice of AMS design and is based on the IOM (Integrated Object-oriented Modeling) paradigm. An AMS, which consists of various machine groups, can produce machine parts in different physical dimensions and lot size. To model such a system, the method which utilizes Sub-PNs are proposed. This enables the models according to part routings. The machine group which causes bottleneck is obtained and modified to relieve the problem. By iterating these steps which consist of modelling, simulation, and performance evaluation, an AMS can e obtained which satisfies the required manufacturing conditions. Finally, the implementation issues of PN modeling are addressed. The approach is the IOM from PN modeling by Sub-PNs and the other is a development of IOM tool for the performance evaluation of AMS.

• ETRI Journal
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• v.45 no.4
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• pp.615-626
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• 2023

Under limited transmission conditions, many factors affect the efficiency of video transmission. During the flight of an unmanned aerial vehicle (UAV), frequent network switching often occurs, and the channel transmission condition changes rapidly, resulting in low-video transmission efficiency. This paper presents an efficient video coding flow for UAVs working in the 5G nonstandalone network and proposes two bit controllers, including time and spatial bit controllers, in the flow. When the environment fluctuates significantly, the time bit controller adjusts the depth of the recursive codec to reduce the error propagation caused by excessive network inference. The spatial bit controller combines the spatial bit mask with the channel quality multiplier to adjust the bit allocation in space to allocate resources better and improve the efficiency of information carrying. In the spatial bit controller, a flexible mini graph is proposed to compute the channel quality multiplier. In this study, two bit controllers with end-to-end codec were combined, thereby constructing an efficient video coding flow. Many experiments have been performed in various environments. Concerning the multi-scale structural similarity index and peak signal-to-noise ratio, the performance of the coding flow is close to that of H.265 in the low bits per pixel area. With an increase in bits per pixel, the saturation bottleneck of the coding flow is at the same level as that of H.264.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• Journal of Korean Society of Transportation
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• v.24 no.4 s.90
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• pp.129-148
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• 2006

The objective of this thesis is to develop a capacity analysis and to develop a methodology to evaluate Level of Service over the entire freeway sections by single MOE (Measure of Effectiveness) This study set forth from a following viewpoint. to analyze entire freeway sections as freeway facility system, it is important to identify the exact point where congestion would occur and the extent of the congestion. Therefore, in this thesis, congestion mechanism on freeways was figured out and congestion analysis methodology was developed. Thereby maximum possible throughput rate and maximum throughput rate in bottleneck sections were calculated and a congestion analysis was carried out. The difference between the new method and existing Procedures is that maximum possible throughput rate and maximum throughput rate. that can be considered as capacities of un-congested and congested flow in the bottleneck section, are variable capacities dependent on demand flow.

• Journal of Biosystems Engineering
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• v.20 no.3
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• pp.262-274
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• 1995

A rice mill pilot plant was designed and developed in the basis of the simulation results on the mill plants. The performance of the developed rice mill plant was evaluated, and the simulation model on the mill system was validated with the experimental data in the mill plant. The results of this study were as followings : 1. A rice mill pilot plant with the capacity of 0.5 t/h was designed and developed. 2. The hulled ratio of the mill plant was 87.3%, and the milled rice recovery and the head rice recovery of the cleaned rice were 74% and 87% , respectively. The degree of milling of the cleaned rice was 10.6% with a high polish. The intensity of the cleaned rice appeared high compared with that of the milled rice in the analysis of whiteness test using an image processing system. 3. The bottleneck, processing time, and production amount of the developed mill system almost coincided with those of the simulation of the rice mill plant. The developed simulation model of the rice mill plant was proven to be applicable to the design of a rice mill plant through experiments.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.3 s.180
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• pp.132-138
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• 2006

With a great requirement of innovation caused by severe competition current companies are encouraged to improve bottleneck areas in production procedure. Specially a chassis line in which assembly processes are mainly carried out manually has the large potential to be automated. The putting of spare tire in trunk in chassis line is still dominated by free dropping method. Through that, parts in trunk such as luggage room lamp, jack and so on were damaged and the complaint of assembler in the next process was occurred due to physical strength. To eliminate these, tile robot system was in this paper developed to place spare tire on the mounting hole in trunk. The movement of robot was synchronized with the velocity of chassis hanger. With this automated system the productivity of the chassis line was increased from the benefits such as simplification of the system using only robot without the mechanically synchronized transport, inserting spare tire into the right position with robot, reduction of damaged parts and production of various type of car.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2001.10a
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• pp.21-24
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• 2001

This study is concerned with the development of efficient p-median approach to nondegenerate cell formation(CF) in group technology(GT) manufacturing. Unlike most of existing CF methodologies allowing degenerate cells or families that contains no parts or machines, this study attempts to find cell configuration where each machine cell contains at least two or more machines processing at least two or more parts so as to fully utilize the similarity in designing and processing parts. Nondegenerate CF seeks to minimize both the exceptional elements outside the diagonal block and the voids within the diagonal block. To find nondegenerate cells, a two-phase p-median methodology is proposed. In phase 1, the classical p-median model is implemented to find initial cells. In phase 2, bottleneck machines and parts are reassigned until no further degenerate cells and families are found. Test results on moderately medium-sized CF problems show the substantial efficiency of the proposed approach.