• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.42-50
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• 2008

The real-time bio-signal monitoring system based on the ZigBee and SIP/RTP has proposed and implemented for telemedicine but that has some problems at the stabilities to transmit bio-signal from the sensors to the other sides. In this paper, we designed and implemented a real-time bio-signal monitoring system that is focused on the reliability and efficiency for transmitting bio-signal at real-time. We designed the system to have enhanced architecture and performance in the ubiquitous sensor network, SIP/RTP real-time transmission and management of the database. The Bluetooth network is combined with ZigBee network to distribute traffic of the ECG and the other bio-signal. The modified and multiplied RTP session is used to ensure real-time transmission of ECG, other bio-signals and speech information on the internet. The modified ECG compression method based on DWLT and MSVQ is used to reduce data rate for storing ECG to the database. Finally we implemented a system that has improved performance for transmitting bio-signal from the sensors to the monitoring console and database. This implemented system makes possible to make various applications to serve U-health care services.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.7 s.349
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• pp.93-103
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• 2006

Network solutions for protecting against worm attacks that complement partial end system patch deployment is a pressing problem. In the content-based worm filtering, the challenges focus on the detection accuracy and its performance enhancement problem. We present a worm filter architecture using the bloom filter for deployment at high-speed transit points on the Internet, including firewalls and gateways. Content-based packet filtering at multi-gigabit line rates, in general, is a challenging problem due to the signature explosion problem that curtails performance. We show that for worm malware, in particular, buffer overflow worms which comprise a large segment of recent outbreaks, scalable -- accurate, cut-through, and extensible -- filtering performance is feasible. We demonstrate the efficacy of the design by implementing it on an Intel IXP network processor platform with gigabit interfaces. We benchmark the worm filter network appliance on a suite of current/past worms, showing multi-gigabit line speed filtering prowess with minimal footprint on end-to-end network performance.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.1
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• pp.26-32
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• 2009

The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit sequentiality in accesses common for such systems and hide the increasing relative cost of disk I/O, existing multi-level storage studies have focused mostly on cache replacement strategies. In this paper, we show that prefetching algorithms designed for single-level systems may have their limitations magnified when applied to multi-level systems. Overly conservative prefetching will not be able to effectively use the lower-level cache space, while overly aggressive prefetching will be compounded across levels and generate large amounts of wasted prefetch. We design and implement a hierarchy-aware lower-level prefetching strategy called PMS(Prefetching strategy for Multi-level Storage system) that applicable to any upper level prefetching algorithms. PMS does not require any application hints, a priori knowledge from the application or modification to the va interface. Instead, it monitors the upper-level access patterns as well as the lower-level cache status, and dynamically adjusts the aggressiveness of the lower-level prefetching activities. We evaluated the PMS through extensive simulation studies using a verified multi-level storage simulator, an accurate disk simulator, and access traces with different access patterns. Our results indicate that PMS dynamically controls aggressiveness of lower-level prefetching in reaction to multiple system and workload parameters, improving the overall system performance in all 32 test cases. Working with four well-known existing prefetching algorithms adopted in real systems, PMS obtains an improvement of up to 35% for the average request response time, with an average improvement of 16.56% over all cases.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.1
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• pp.1-8
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• 2021

This study developed low-cost and high-efficiency pavement condition monitoring technology to produce the key information required for pavement management. A noise and artificial intelligence-based monitoring system was devised to compensate for the shortcomings of existing high-end equipment that relies on visual information and high-end sensors. From idea establishment to system development, functional definition, information flow, architecture design, and finally, on-site field evaluations were carried out. As a result, confidence in the high level of artificial intelligence evaluation was secured. In addition, hardware and software elements and well-organized guidelines on system utilization were developed. The on-site evaluation process confirmed that non-experts could easily and quickly investigate and visualized the data. The evaluation results could support the management works of road managers. Furthermore, it could improve the completeness of the technologies, such as prior discriminating techniques for external conditions that are not considered in AI learning, system simplification, and variable speed response techniques. This paper presents a new paradigm for pavement monitoring technology that has lasted since the 1960s.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.11-20
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• 2007

A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].

• Journal of the Korea Society of Computer and Information
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• v.14 no.11
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• pp.97-103
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• 2009

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.

• The Journal of the Convergence on Culture Technology
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• v.8 no.3
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• pp.449-455
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• 2022

The Colony of Selaginella involvens (Sw.) Spring in Sanyang-myeon, Mungyeong-si, can be divided into five types, and in the past, it was said that Selaginella involvens (Sw.) Spring formed colonies throughout the colony and grew naturally, but now it remains only in some sections. It was found that the Selaginella involvens (Sw.) Spring colony was damaged by artificial and natural factors, and as an artificial factor, the Selaginella involvens (Sw.) Spring was proven to be effective for medicinal and cremation, and many people were damaging the Selaginella involvens (Sw.) Spring colony without permission. Naturally, vines thrive and Selaginella involvens (Sw.) Spring die, and the reality is that the entire colony of Selaginella involvens (Sw.) Spring is in danger of being damaged if maintenance is not performed. On the other hand, there are sections that reproduce with symbiosis with some herbaceous plants, so it is necessary to plan and implement conservation strategies. In order to preserve the Selaginella involvens (Sw.) Spring colony, CCTV is needed to prevent artificial damage, and on the contrary, install facilities such as fences can easily burn up and create worse scenery, so it can preserve the good environment, restore recoverable areas, and install supplementary buffer zones.

• Journal of the Korea Society for Simulation
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• v.33 no.2
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• pp.1-11
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• 2024

A cyber-physical system is a technology that connects the physical systems of a manufacturing environment with a cyber space to enable simulation. One of the major challenges in this technology is the seamless communication between these two environments. In complex manufacturing processes, it is crucial to adapt to various protocols of manufacturing equipment and ensure the transmission and reception of a large volume of data without delays or errors. In this study, we propose a method for constructing agent models for real-time simulation-capable cyberphysical systems. To achieve this, we design data collection units as independent agent models and effectively integrate them with existing simulation tools to develop the overall system architecture. To validate the proposed structure and ensure reliability, we conducted empirical testing by integrating various equipment from a real-world smart microfactory system to assess the data collection capabilities. The experiments involved testing data delay and data gaps related to data collection cycles. As a result, the proposed approach demonstrates flexibility by enabling the application of various internal data collection methods and accommodating different data formats and communication protocols for various equipment with relatively low communication delays. Consequently, it is expected that this approach will promote innovation in the manufacturing industry, enhance production line efficiency, and contribute to cost savings in maintenance.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.3
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• pp.240-247
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• 2001

Java is a promising runtime environment for embedded systems because it has many advantages such as platform independence, high security and support for multi-threading. One of the most famous Java run-time environments, Sun's ($PersonalJave^{TM}$) is based on Truffle architecture, which enables programmers to design various GUIs easily. For this reason, it has been ported to various embedded systems such as set-top boxes and personal digital assistants(PDA's). Basically, Truffle uses heavy-weight window managers such as Microsoft vVin32 API and X-Window. However, those window managers are not adequate for embedded systems because they require a large amount of memory and disk space. To come up with the requirements of embedded systems, we adopt Microwindows as the platform graphic system for Personal] ava A WT onto Embedded Linux. Although Microwindows is a light-weight window manager, it provides as powerful API as traditional window managers. Because Microwindows does not require any support from other graphics systems, it can be easily ported to various platforms. In addition, it is an open source code software. Therefore, we can easily modify and extend it as needed. In this paper, we implement Personal]ava A WT using Microwindows on embedded Linux and prove the efficiency of our approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.