• International journal of advanced smart convergence
• /
• 제4권1호
• /
• pp.1-10
• /
• 2015

Automotive Theft has been an obstinate problem around the world. Design and manufacture of anti-theft systems have become more and more complex due to the rise in complexity of theft in the system. Most of the anti-theft systems available in the market, are the alarm types which audibly deter some thieves away but do not prevent one's car from being stolen and even are not good enough to meet the growing complexity of theft in the country. This paper presents a simple and an efficient anti-theft system which provides improved security by the use of efficient access mechanisms and immobilization systems. This security system can immobilise an automobile and its key auto systems through remote control when it is stolen. It hence deters thieves from committing the theft. It also effectively prevents stealing of key auto systems for reselling by introducing four layers of security features written in the form of firmware and embedded on the Electronic Control Units (ECUs). The particulars of system design and operation are defined in the paper. The experimental outcomes show that this system is practicable and the owner can steadily control his vehicle within a few seconds.

• 한국정보전자통신기술학회논문지
• /
• 제2권1호
• /
• pp.37-42
• /
• 2009

디지털 신호 처리 분야에서 디지털 필터는 필수불가결한 요소이다. 디지털 필터는 이진수의 곱셈 및 덧셈을 기본으로 하는 것으로 많은 연산량을 필요로 한다. 디지털 필터 내의 곱셈기는 VLSI 기술을 이용한 디지털 필터의 설계에 있어 반도체 칩 내부의 넓은 영역을 차지하고 전력의 대부분을 소비하며, 필터의 critical path를 결정하여 필터의 성능을 결정하는 중요한 요소로서 작용 한다. 본 연구에서는 특히 디지털 필터의 복잡성(complexity)를 해소하고 critical path를 줄여 필터의 연산속도를 증가시키기 위한 방법으로 2의 보수로서 표현되는 이진수를 CSD(canonical signed digit)와 MSD(minimal signed digit)로 동시에 변환하여 표현하는 방법을 제안하였다. 제안된 방법은 VHDL로 구현하고 임의의 필터에 적용하여 필터의 critical path가 감소하는 것을 보였다.

• ETRI Journal
• /
• 제30권3호
• /
• pp.365-376
• /
• 2008

This paper presents the design and implementation of a hyperelliptic curve cryptography (HECC) coprocessor over affine and projective coordinates, along with measurements of its performance, hardware complexity, and power consumption. We applied several design techniques, including parallelism, pipelining, and loop unrolling, in designing field arithmetic units, group operation units, and scalar multiplication units to improve the performance and power consumption. Our affine and projective coordinate-based HECC processors execute in 0.436 ms and 0.531 ms, respectively, based on the underlying field GF($2^{89}$). These results are about five times faster than those for previous hardware implementations and at least 13 times better in terms of area-time products. Further results suggest that neither case is superior to the other when considering the hardware complexity and performance. The characteristics of our proposed HECC coprocessor show that it is applicable to high-speed network applications as well as resource-constrained environments, such as PDAs, smart cards, and so on.

• Journal of Electrical Engineering and Technology
• /
• 제12권6호
• /
• pp.2365-2377
• /
• 2017

This paper addresses two interrelated problems concerning the tracking control of pod propulsion unmanned surface vessel (USV), namely, the modeling of pod propulsion USV, and tracking controller design. First, based on MMG modeling theory, the model of pod propulsion USV is derived. Furthermore, a practical adaptive neural tracking controller is proposed by backstepping technique, neural network approximation and adaptive method. Meanwhile, unlike some existing tracking methods for surface vessel whose control algorithms suffer from "explosion of complexity", a novel neural shunting model is introduced to solve the problem. Using a Lyapunov functional, it is proven that all error signals in the system are uniformly ultimately bounded. The advantages of the paper are that first, the underactuated characteristic of pod propulsion USV is proved; second, the neural shunting model is used to solve the problem of "explosion of complexity", and this is a combination of knowledge in the field of biology and engineering; third, the developed controller is able to capture the uncertainties without the exact information of hydrodynamic damping structure and the sea disturbances. Numerical examples have been given to illustrate the performance and effectiveness of the proposed scheme.

• 한국실내디자인학회논문집
• /
• 제31호
• /
• pp.56-63
• /
• 2002

This study intends to prepare a system that can be used, by applying digital technique, in analyzing complexity of architectural forms that have been visualized by the correlation based on the distribution chart made in accordance with profile lines. The profile lines are derived from the edge analysis of the architectural forms, simplified based on the visual theory. For the purpose, this study was conducted in the following ways: First, problems of the existing models for the elevation analysis were examined along with formal analysis based on visual recognition to consider the profile lines derived from the forms. Secondly, in elevation analysis, profile lines were derived by digital method to measure them qualitatively. To verify the objectivity of the measured data value, a survey was conducted based on the adjective cataloging method, and the correlation of the survey result and analyzed data was analyzed to verify the validity of the derived data. Thirdly, supplementation for the problems deducted from experiments and the possibility to use it in designing were suggested. Digital method has many advantages over the conventional analyzing system in deriving precise data value by excluding subjectivity. It also allows various analytical methods in analyzing numerous data repeatedly. Diversified models and methods of analysis considering numerous factors arising in the process of designing remain assignments to research in future.

• 대한전자공학회논문지SP
• /
• 제48권5호
• /
• pp.123-128
• /
• 2011

본 논문에서는 레이더의 탐지 알고리즘에 적용되는 CA-CFAR 알고리즘을 설계하였다. CFAR 알고리즘의 제곱평균 연산을 위해 근사화 기법을 사용하였으며, 고정 소수점을 이용하여 관련 연산을 처리하였다. 이러한 구조는 하드웨어 복잡도를 줄일 뿐 아니라 계산량을 감소시킬 수 있다. CFAR 연산은 슬라이딩 윈도우 기법을 기반으로 하는데, 이를 고속으로 처리하기 위해 동시 병렬 처리 가능한 다중 윈도우 방식도 제안하였다. 제안된 CA-CFAR 프로세서는 실제 FPGA를 통해 합성되어지고 구현되었다. 또한 FPGA 내에서 제공한 라이버러리를 이용한 제곱평균 연산 방법과 성능 비교를 하였다. 검증 결과 제안된 하드웨어 구조는 399MHz까지 동작가능하며, 전체 계산 시간은 약 70% 향상됨을 확인 할 수 있다.

• 전자공학회논문지C
• /
• 제34C권3호
• /
• pp.1-10
• /
• 1997

We present an approach to high-level synthesis for a specific target architecture-partitioned bus architecture. In this approach, we have specific goals of minimizing data transfer length and number of buses in addition to common synthesis goals such as minimizing number of control steps and satisfying given resource constraint. Minimizing data transfer length and number of buses can be very important design goals in the era of deep submicron technology in which interconnection delay and area dominate total delay and area of the chip to be designed. in partitioned bus architecture, to get optimal solution satisfying all the goals, partitioning of operation nodes among segments and ordering of segments as well as scheduling and allocation/binding must be considered concurrently. Those additional goals may impose much more complexity on the existing high-level synthesis problem. To cope with this increased complexity and get reasonable results, we have employed two ideas in ur synthesis approach-extension of the target architecture to alleviate bus requirement for data transfer and adoption of genetic algorithm as a principal methodology for design space exploration. Experimental results show that our approach is a promising high-level synthesis mehtodology for partitioned bus architecture.

• 복식
• /
• 제59권2호
• /
• pp.29-41
• /
• 2009

Perception between real object and recognized subject of human on objective subject is not the same. The reason Is that individual perception of visual design components are transmitted as the image of whole. It is required process of visual perception. Therefore, I developed the vision of seeing image of pattern which is based on Gestalt visual perception theory in clothes. The summary of this study's results is like followings. Extremely antagonistic terms which are specialized by formative characteristics of formative components are clearness and blur of outline/ fixed shape and non-fixed shape/ visuality and tangibility of representation/ simplicity and complexity of structure/ invariability and variability of mobility/ symmetry and asymmetry of arrangements singularity and plurality of group number. The expression of motive shows that clearness, fixed shape, visuality and simplicity pursuit Determination image, and blur, non-fixed shape, tangibility and complexity pursuit Ambiguity image. The arrangements of motive shows that invariability, symmetry and singularity pursuit Order image, and variability asymmetry and plurality pursuit Disorder image. Therefore, the standard of the coordinator of Pattern image positioning is established as Determination and Ambiguity of motive are X-axis, and Order and Disorder of pattern are Y-axis. As the frame of Pattern image positioning, four separated dimensions have made.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제8권7호
• /
• pp.2464-2479
• /
• 2014

Multi-view video coding is an international encoding standard that attains good performance by fully utilizing temporal and inter-view correlations. However, it suffers from high computational complexity. This paper presents a fast encoder design to reduce the level of complexity. First, when the temporal correlation of a group of pictures is sufficiently strong, macroblock-based inter-view prediction is not employed for the non-anchor pictures of B-views. Second, when the disparity between two adjacent views is above some threshold, frame-based inter-view prediction is disabled. Third, inter-view prediction is not performed on boundary macroblocks in the auxiliary views, because the references for these blocks may not exist in neighboring views. Fourth, finer partitions of inter-view prediction are cancelled for macroblocks in static image areas. Finally, when estimating the disparity of a macroblock, the search range is adjusted according to the mode size distribution of the neighboring view. Compared with reference software, these techniques produce an average time reduction of 83.65%, while the bit-rate increase and peak signal-to-noise ratio loss are less than 0.54% and 0.05dB, respectively.

• 한국실내디자인학회논문집
• /
• 제41호
• /
• pp.146-154
• /
• 2003

The purpose of this study is, According to society changing fast, human life is changing in the direction of complexity and variety, the middle class and multiple structure have been generated in relation between architecture and function. Accordingly, considering the analyzed elements of the main floor space planning and relation of the factors in space planning of Seoul s public libraries. The Public Library is variety of function is abstracted to the plan for Space Composition Form from future public library, analysis of “This point of user, how to composition is the space of different function” and “How to is the connection between the educational function and the other function, complexity of space.” With above distinctive themes and the research, the typology of public library in seoul city, At the first, the research shows that the public library is 8 type, and high in typology of “TYPE 7 (A3-B2-Cl)”. Secondary, There appears public library, such as in the satisfaction of the One-Function-User is high in “TYPE 3 (A1-B2-C3)”, in the satisfaction over the Two-Function-User is high in “TYPE 6 (A3-B1-C1)”