• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.40 no.9
• /
• pp.827-832
• /
• 2012

In this paper, we will design the speed measurement board of LEO Satellite's reaction wheel which has two speed measuring methods as M-Method type and T-Method type. therefore we can use the advantage of two methods. and we will verify the availability of design on the on-board computer at the real LEO Satellite(KOMPSAT-3). In the reaction wheels satellite that can change the satellite's attitude is one of the leading drivers by the rotational inertia of the motor will perform attitude control. Reaction methods for detecting wheel rotation speed generated during a certain period T internal reaction wheel tacho pulse counting M-Method to detect wheel speed and wheel tacho pulses are generated by measuring the time between the detection rate can be divided into T-Method. M-method is simple to implement and benefit measurement time is constant, but slow fall in the velocity measurement accuracy is a disadvantage. In contrast, the time between tacho pulses to measure the T-Method to measure the precise speed at low speed and to measure the time delay is small, has the advantage. However, this method also in the actual implementation and the complexity of the operation at different speeds depending on the speed of operation has the disadvantage.

• Journal of the Korean Geotechnical Society
• /
• v.28 no.11
• /
• pp.33-40
• /
• 2012

The design of Piled Raft foundations considering the load sharing between raft and piles provides a more economical solution than the conventional design approach based on bearing capacity of piles only. Generally, numerical methods are used to analyze the behavior of Piled Rafts due to its complexity and load sharing ratio is also estimated by numerical methods about some limited cases under specific load level and soil conditions. In this study, a method to estimate the load sharing between the raft and piles was developed which is based on load-settlement characteristics of foundation elements. Normalized load-settlement curves of the raft and pile groups were derived individually, and the relationship between load sharing ratio and foundation settlement was proposed by using these curves. For each load-settlement curves, hyperbolic type was adopted in order to describe the non-linear behavior of foundations. Centrifuge test results were compared with the results from proposed method, and the trends of variation of load sharing ratio with settlement presented from both were similar.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.11A
• /
• pp.1104-1109
• /
• 2005

In this paper, a Ka-band harmonic mixer is designed and fabricated on the base of the multiplier theory that there is a bias point to maximize the third harmonic order($3f_{LO}$) with respect to a fundamental LO frequency($f_{LO}$), which can make the high-order mixing element($f_{RF}{\pm}3f_{LO}$) to be greater than other mixing elements, Pumping a RF frequency($f_{RF}$) and LO frequency($f_{LO}$). The harmonic mixer by the proposed design method is fabricated by using a commercial GaAs MESFET device with a plastic package and overcome these disadvantages that a conventional mixer in Ka-band suffer from a high cost, inefficient productivity and circuit complexity. The harmonic mixer have a -10 dB conversion loss at the IF Sequency($3f_{LO}-f_{RF}$=1.0GHz) by selecting a gate bias voltage for the maximum third-order LO harmonic element($3f_{LO}$=34.5 GHz) as pumping LO frequency($f_{LO}$=11.5 GHz) With respect to RF Sequency ($f_{RF}$=33.5GHz)

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.12
• /
• pp.60-69
• /
• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.2
• /
• pp.335-342
• /
• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.875-878
• /
• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.4 no.1
• /
• pp.267-282
• /
• 2000

With the development of computer&network technology and the growth of its dependance, computer failures not only lose human and material resources but also make organization's competition weak as a side-effect of information society. Therefore, people consider computer security as important factor. Intrusion Detection Systems (IDS) detect intrusions and take an appropriate action against them in order to protect a computer from system failure due to illegal intrusion. A variety of methods and models for IDS have been developed until now, but the existing methods or models aren't enough to detect intrusions because of the complexity of computer network the vulnerability of the object system, insufficient understanding for information security and the appearance of new illegal intrusion method. We propose a new IDS model to be suitable at the information system organized by homogeneous hosts and design for the IDS model and implement the prototype of it for feasibility study. The IDS model consist of many distributed unit sensor IDSs at homogeneous hosts and if any of distributed unit sensor IDSs detect anomaly system call among system call sequences generated by a process, the anomaly system call can be dynamically shared with other unit sensor IDSs. This makes the IDS model can effectively detect new intruders about whole information system.

• Journal of Advanced Navigation Technology
• /
• v.25 no.5
• /
• pp.426-432
• /
• 2021

Continuous wave (CW) Doppler radar has the advantage of being able to solve the privacy problem unlike camera and obtains signals in a non-contact manner. Therefore, this paper proposes a human activity recognition (HAR) system using CW Doppler radar, and presents the hardware design and implementation results for acceleration. CW Doppler radar measures signals for continuous operation of human. In order to obtain a single motion spectrogram from continuous signals, an algorithm for counting the number of movements is proposed. In addition, in order to minimize the computational complexity and memory usage, binarized neural network (BNN) was used to classify human motions, and the accuracy of 94% was shown. To accelerate the complex operations of BNN, the FPGA-based BNN accelerator was designed and implemented. The proposed HAR system was implemented using 7,673 logics, 12,105 registers, 10,211 combinational ALUTs, and 18.7 Kb of block memory. As a result of performance evaluation, the operation speed was improved by 99.97% compared to the software implementation.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.20 no.4
• /
• pp.564-570
• /
• 2019

Although some studies have been attempted to utilize 3D spatial information for fire safety and disaster management, it is still not enough to apply it to actual work. Especially, in case of multi-use facilities, many facilities are more vulnerable to rapid response in the event of a disaster due to complexity of facilities, diversity of usage, and specificity of users. In this paper, we propose a method to develop a 3D safety status information platform that combines 3D spatial information and time - varying safety status information for efficient disaster management of multi-use facilities. In detail, first, we analyze the use cases of existing disaster management platform and the needs of business users. Second, based on the analyzed results, target facilities were selected and possible scenarios were created. Finally, we developed platform architecture design and service development strategy. The research results will be used as a basis for future 3D safety status information platform development. This will contribute to improving the safety of multi-use facilities and minimizing damage to disaster vulnerable groups.

• Journal of Navigation and Port Research
• /
• v.47 no.4
• /
• pp.256-270
• /
• 2023

In this study, a sliding mode (SM) controller for dynamic positioning (DP) was specifically designed for a turret connection operation of a ship or an offshore structure in which an arbitrary point on the structure could be controlled as the motion center instead of the center of mass. The SM controller allows control of the arbitrary point and provides capability to manage uncertainties in the dynamics of ships and offshore structures, external forces caused by unknown changing marine environments, and transient performance of DP systems. The Jacobian matrix included in kinematic equations of the controlled object was modified to design the SM controller to control based on an arbitrary point of ships or offshore structures. To ensure robustness of the controller, the Lyapunov stability theory was applied in the design of the SM controller. In general, for robustness in DP control, gain scheduling based on a proportional-derivative (PD) control algorithm is employed. However, finding appropriate gains for gain scheduling complicates the application of DP systems. Therefore, in this study, the SM control algorithm was considered to mitigate the complexity of the DP controller for ships and offshore structures. To validate the proposed SM control algorithm, time-domain simulations were conducted and utilized to evaluate the performance of the control algorithm. The effectiveness of the proposed SM controller was assessed by comparing simulation results with results of a conventional PD control algorithm applied in DP control.