• Proceedings of the IEEK Conference
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• summer
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• pp.302-309
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• 2004

The transmission capacity of wireless communication systems may become dramatically high by employ multiple transmit and receive antennas with space-time coding techniques appropriate to multiple transmit antennas. For large number of transmit antennas and at high bandwidth efficiencies, the receiver may become too complex whenever correlation across transmit antennas is introduced. Reducing decoding complexity at receiver by combining array processing and space-time codes (STC) helps a communication system using STC to overcome the big obstacle that prevents it from achieving a desired high transmission rate. Multi-carrier CDMA (MC-CDMA) allows providing good performance in a channel with high inter-symbol interference. Antenna array, STC and MC-CDMA system have a similar characteristic that transmit-receive data streams are divided into sub-streams. Thus, there may be a noticeable reduction of receiver complexity when we combine them together. In this paper, the combination of array processing and STC in MC-CDMA system over slow selective-fading channel is investigated and compared with corresponding existing MC-CDMA system using STC. A refinement of this basic structure leads to a system design principle in which we have to make a trade off between transmission rate, decoding complexity, and length of spreading code to reach a given desired design goal.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.371-374
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• 2000

This paper proposes a 16-bit ${\times}$ 16-bit multiplier for 2 twos-complement binary numbers with tree-like structure and implements it on a FPGA. The space and time complexity analysis shows that the 16-bit Tree-like multiplier represents lower circuit complexity and computes more quickly than both Booth array multiplier md Modified array multiplier.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.17 no.30
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• pp.185-192
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• 1994

The complexity and consistency are important factors that affect human information processing in use of product. In this study, complexity and consistency of product(remote controller) are measured by Task Action Grammar(TAG) model. Also, new design alternative of the user interface is presented and evaluated. The results show that the consistent system and the good correspondence between hierarchical structure of system and user's mental model lead to the reduction of errors and enhanced user's performance.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.965-966
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• 2006

As billion transistors system-on-chip (SoC) design becomes a reality, the productivity gap between rapidly increasing design complexity and designer productivity lagging behind is becoming a more serious problem to be solved. To reduce the gap, we present a system that generates executable transaction level models automatically. It speed up the SoC design space exploration process at various abstraction levels.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.9
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• pp.896-903
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• 2011

In this paper, a co-design method for JPEG2000 video compression system using DSP and FPGA is presented. By profiling the complexity of JPEG2000 algorithm, it is noticed that a MQ-coder is the most complex part. Thus, we implement the MQ-coder on FPGA for the parallel processing using VHDL to reduce the complexity. In order to verify the performance of the MQ-coder, JBIG2 standard test vector and images are used. The experimental results show that the proposed MQ-coder enhances the processing time approximately 3 times compared with the previous software MQ-coder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.105-113
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• 2000

This paper proposes the optimal design method of PSF(pulse shaping filter) with fixed-point coefficients, often used in digital communication system. Though RCF (Raised Cosine Filter) and Root-Squared RCF have less attenuation in stopband and are designed with floating point coefficients, those are selected by the reason that the design is simple. In this paper, 1 introduce the optimal design method for fixed point PSF including Root Squared type by using mixed integer linear programming. Through some design examples, it is shown that the proposed method better performs in ISI and requires less complexity. The complexity of the proposed filter is reduced to 20% as compared to conventional RCF and Root Squared RCF. For IS-95, that is the standard of CDMA system, the proposed filter reduces ISI up to 75% compared to the standard transmission filter.

• Journal of Power System Engineering
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• v.1 no.1
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• pp.154-161
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• 1997

Because of the complexity of the flower design of roll forming process, in which the flat strip is progressively deformed by successive sets of profiled rolls, a computer-aided design system for the flower design has been developed. It is programmed in AutoLISP and DCL(Dialogue Control Language) of AutoCAD. It has been found that the system is helpful in saving the time and effort required to design the flower of the product to be roll-formed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.95-117
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• 2006

In this paper, we describe the optimization of the link-level performance and the complexity of floating-point and fixed-point methods in IEEE 802.16e OFDMA/TDD mobile modem. In floating-point design, we propose the channel estimation methods for downlink traffic channel and select the optimized method using computer simulation. So we also propose efficent algorithms for time and frequency synchronization, Digital Front End and CINR estimation scheme to optimize the system performance. Furthermore, we describe fixed-point method of uplink traffic and control channels. The superiority of the proposed algorithm is validated using the performances of Detection, False Alarm, Missing Probability and Mean Acquisition Time, PER Curve, etc. For fixed-point design, we propose an efficient methodology for optimized fixed-point design from floating-point At last, we design fixed-point of traffic channel, time and frequency synchronization, DFE block in uplink and downlink. The tradeoff between performance and complexity are optimized through computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12A
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• pp.1387-1395
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• 2004

Turbo decoder inherently requires large memory and intensive hardware complexity due to iterative decoding, despite of excellent decoding efficiency. To decrease the memory space and reduce hardware complexity, various design issues have to be discussed. In this paper, various design issues on Turbo decoder are investigated and the tradeoffs between the hardware complexity and the performance are analyzed. Through the various simulations on the fixed-length analysis, we decided 5-bits for the received data, 6-bits for a priori information, and 7-bits for the quantization state metric, so the performance gets close to that of infinite precision. The MAX operation which is the main function of Log-MAP decoding algorithm is analyzed and the error correction term for MAX* operation can be efficiently implemented with very small hardware overhead. The size of the sliding window was decided as 32 to reduce the state metric memory space and to achieve an acceptable BER.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.3
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• pp.85-90
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• 2003

This paper proposes a modular multiplier based on LFSR (Linear Feedback Shift Register) architecture with efficient area complexity over GF(2/sup m/). At first, we examine the modular exponentiation algorithm and propose it's architecture, which is basic module for public-key cryptosystems. Furthermore, this paper proposes on efficient modular multiplier as a basic architecture for the modular exponentiation. The multiplier uses AOP (All One Polynomial) as an irreducible polynomial, which has the properties of all coefficients with '1 ' and has a more efficient hardware complexity compared to existing architectures.