• 한국정보통신학회논문지
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• 제9권1호
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• pp.134-139
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• 2005

본 논문은 양극 형조 방전 가공기를 제작하고 그 성능을 평가하였다. 설계 구현된 형조 방전 가공기는 극간 전압 제어기 설계와 서보 모터 제어기 설계 두 부분으로 이루어져 있고, 시뮬레이션을 통해 검증하고 제작하였다. 구현된 방전 가공기의 성능을 기존의 방전 가공기와 가공속도와 가공 표면의 거칠기를 비교 평가하였다. 연구의 결과로는 설계된 가공기가 가공속도와 면조도에서 개선된 결과를 얻었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.497-500
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• 2005

This paper presents a design of a hybrid sensor chip which integrates an A/D converter module and a phase measurement module for measuring power line phase. Recursive sliding DFT based phase measurement module is designed using time shared multiplier which can reduce the size of SoC implementation. A/D converter is based on the sigma delta modulation in order to minimize the implementation space of the analog part and designed to obtain 8-bit resolution. Computer simulations and FPGA implementation are performed to verify hybrid sensor chip design. The hybrid sensor chip for 4-channel power line phase measurement is fabricated by using 0.35 micrometer CMOS process.

• Journal of Information Processing Systems
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• 제13권1호
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• pp.26-39
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• 2017

The need for embedded devices to be able to exchange information with each other and with data centers is essential for the advent of the Internet of Things (IoT). Several existing communication protocols are designed for small devices including the message-queue telemetry transport (MQTT) protocol or the constrained application protocol (CoAP). However, most of the existing implementations are convenient for computers or smart phones but do not consider the strict constraints and limitations with regard resource usage, portability and configuration. In this paper, we report on an industrial research and development project which focuses on the design, implementation, testing and deployment of a MQTT module. The goal of this project is to develop this module for platforms having minimal RAM, flash code memory and processing power. This software module should be fully compliant with the MQTT protocol specification, portable, and inter-operable with other software stacks. In this paper, we present our approach based on abstraction layers to the design of the MQTT module and we discuss the compliance of the implementation with the requirements set including the MISRA static analysis requirements.

• International Journal of Contents
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• 제17권2호
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• pp.9-19
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• 2021

The purpose of this survey-based study was to investigate high school students' perceptions of mathematics teachers' implementation of Universal Design for Learning (UDL)-based practices and technology in their mathematics classes in 2017. A total of 303 high school students in South Korea participated in this online survey on teachers' use of technology for instructional practices, the frequency of technology tool use, and the meeting of UDL guidelines in mathematics instruction. According to frequency analysis, high school students generally perceived their teachers' mathematics teaching as somewhat positive in providing multiple means of representation, action and expression, and engagement. However, mathematics teachers' implementation of technology tools in their mathematics classes was generally limited. This study indicated significant and positive relationships between variables regarding the use of technology tools and teachers' efforts to follow the UDL guidelines. Applying the Chi-squared test, we further examined how each survey result differed according to high school students' academic achievements and grade levels.

• ETRI Journal
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• 제27권5호
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(3)
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• pp.43-46
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• 2001

This thesis proposes the design method of intelligent robot agent system and deals with the implementation of the system which is able to produce key internet statistics. It is believed that the statistics lead to effective investment from internet industry on its development. The system consists of robot agent process module, statistics production module and management module, and has an algorithm that can produce periodically the number of domestic homepages, active domain using .kr or gTLD and intenet hosts. It provides the result of the implementation and performance of the system as well.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.523-526
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• 1998

In an ongoing project at ETRI-CSTL, A debugger for distributed programs that run on a varied collection of machines is being built. To build such debugger, a clientserver model is incorporated. This strategy enables us to provide a unified user interface and isolate debugger core from the user interface. Several debugging servers running on a diverse set of platforms permit the implementation of a distributed debugger for heterogeneous environment, and the single debugging client provides unified debugging concept and graphical user interface over various servers. Also, the precise specification of the interaction protocol between the client and server facilitates client to be paired with a variety of server implementantations. This paper describes the design and implementation of our debugger, concentrating on the system architecture.

• ETRI Journal
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• 제26권4호
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• pp.367-370
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• 2004

A new transmission system is necessary for the Digital Multimedia Broadcasting (DMB) service in Korea. Therefore, in this paper, we propose a new architecture for the implementation of a DMB transmission system based on Eureka-147. We describe the design and implementation of the Ensemble remultiplexer, which is essential to the proposed system for remultiplexing ETI frames and MPEG-2 transport streams. The proposed system provides a solution with high flexibility and low cost for multimedia broadcasting service. The functions of this transmission system have been verified by using our DMB receiver and other related systems.

• 한국사이버테러정보전학회:학술대회논문집
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• 한국사이버테러정보전학회 2004년도 제1회 춘계학술발표대회
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• pp.59-64
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• 2004

본 논문에서는 SEED와 Triple-DES 알고리즘을 구현하는 통합 대칭키 암호칩을 설계하고 구현하였다. 시스템 설계 기술 언어인 VHDL(VHSIC Hardware Description Language)로 설계하였으며, 다양한 분야에 응용할 수 있도록 4가지 동작 모드를 지원한다. 자일링스(Xilinx)사의 Virtex-E XCV2000E BG560을 대상으로 설계하였으며 Xilinx Foundation Series 3.li을 이용하여 기능 시뮬레이션과 타이밍 시뮬레이션을 통해 FPGA 구현 시 데이터의 암호화 복호화 결과를 확인하였다.

• 정보처리학회논문지A
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• 제8A권1호
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• pp.1-8
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• 2001

This paper describes the design and implementation of C standard library for real-time operating system Q+, that is being developed for the internet appliance. The C library in the real-time operating system should be defined according to the standard interface and support the concurrent execution of threads. The implemented C standard library is reentrant and follows POSIX.l standard interface. And, the C standard library functions, which are adequate to the Q+ application and commonly provided by commercial real-time operating systems, are selected among POSIX.l standard functions. The C standard library is implemented on the Q+ kernel and D-TV set-top box according to the implementation sequence, which is determined by analyzing the relation of function calls.