• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.309-314
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• 2011

As a system becomes more complex, a design relies more heavily on a methodology based on high-level abstraction and functional verification. SystemVerilog includes characteristics of hardware design language and verification language in the form of extensions to the Verilog HDL. However, the OOP of System Veri log does not allow multiple inheritance. In this paper, we propose adoption of SystemC to introduce multiple inheritance. After being created, a SystemC unit is combined with a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes a design of a verification environment simple and easy through source code reuse. Moreover, a verification environment including SysemC unit has a benefit of reconfigurability due to OOP.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.173-176
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• 2000

Silicon semiconductor technology agree that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduce verification time. This Paper describe the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.323-339
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• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.91-98
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• 1992

In this paper, a new heuristic algorithm for designing combinational circuits suitable for verification testing is presented. The design method consists of argument reduction, input partitioning, output partitioning, and logic minimization. A new heuristic algorithm for input partitioning and output partitioning is developed and applied to designing combinational circuits to demonstrate its effectiveness.

• Smart Media Journal
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• v.1 no.1
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• pp.48-52
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• 2012

A reliable test of offshore plant hold a key post in offshore engineering technology. The offshore self-supporting of process module design and basic design technology needs engineering verification based on the reliable test. And also reliable verification test data is very important. Therefore, verification test system for offshore installation simulation is necessary. This paper explains design of data acquisition system and control system based on the parameter of measured and controlled variable which is for establishing offshore installation simulation system.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.5
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• pp.675-683
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• 2018

In this paper, we have proposed a design and verification methods of electrical system and power loads for unmaned aeriel vehicles(UAVs) through electrical load analysis. In order to meet a UAV system requirement and electrical system specifications, we have designed an electrical power system for efficient power supply and distribution and have theoretically analyzed the power loads according to the power consumption and power bus design of UAV. Using electrical system rig, the designed electrical power system has been experimentally verified. Also, we have performed several flight tests to verify the UAV electrical system and power loads. It is concluded that the proposed design and verification method of electrical system for UAV system.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.585-588
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• 2004

This paper describes design and verification of the motion estimation and compensation unit using full search algorithm. Video processor is the key device of video communication systems. Motion estimation is the key module of video processor. The technologies of motion estimation and compensation unit are the core technologies for wireless video telecommunications system, portable multimedia systems. In this design, Verilog simulator and logic synthesis tools are used for hardware design and verification. In this paper, motion estimation and compensation unit are designed using FPGA, coded in Verilog HDL, and simulated and verified using Xilinx FPGA.

• Corrosion Science and Technology
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• v.6 no.3
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• pp.90-95
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• 2007

Cathodic protection technology has been widely used on ship's outer hull and inner side of ballast water tanks as a supplementary corrosion protection measure in combination with protective organic coatings. Impressed current cathodic protection system is typically opted for the ship's hull and, sacrificial anode system, for ballast water tanks. The anticipation and interest in cathodic protection system for ships has been surprisingly low-eyed to date in comparison with protective coatings. Computational analysis for the verification of cathodic protection design has been tried sometimes for offshore marine structures, however, in commercial shipbuilding section, decades old design practice is still applied, and no systematic or analytical verification work has been done for that. In this respect, over-rotection from un-erified initial design protocol has been also concerned by several experts. Especially, it was frequently reported in sacrificial anode system that even after full design life time, anode was remaining nearly intact. Another issue for impressed current system, for example, is that the anode shield area design for ship's outer hull should be compromised with actual application situation, because the state-of-the-art design equation is quite impractical from the applicator's stand. Besides that, in this study, some other critical design issues for sacrificial anode and impressed current cathodic protection system were discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.38-49
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• 2006

In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.

• Nuclear Engineering and Technology
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• v.56 no.4
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• pp.1330-1338
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• 2024

Information on isotopic composition and geometric structure is necessary for identifying a true warhead. Nevertheless, such classified information should be protected physically or electronically. With a novel Hash encryption algorithm, this paper presents a Monte Carlo-based design of a neutron activation analysis verification module. The verification module employs a thermal neutron source, a non-uniform mask (physically encrypting information about isotopic composition and geometric structure), a gamma detector array, and a Hash encryption algorithm (for electronic encryption). In the physical field, a non-uniform mask is designed to distort the characteristic gamma rays emitted by the inspected item. Furthermore, as part of the Hash algorithm, a key is introduced to encrypt the data and improve the system resolution through electronic design. In order to quantify the difference between items, Hamming distance is used, which allows data encryption and analysis simultaneously. Simulated inspections of simple objects are used to quantify system performance. It is demonstrated that the method retains superior resolution even with 1% noise level. And the performances of anti-statistical attack and anti-brute force cracking are evaluated and found to be very excellent. The verification method lays a solid foundation for nuclear disarmament verification in the upcoming era.