• 제목/요약/키워드: Design Verification Process

검색결과 656건 처리시간 0.028초

고효율조명기기 프로그램 성과의 계량 및 검증 기법의 개발 (Development of a Measurement and Verification Scheme for Efficient Lighting Program)

  • 조기선;박종진;이창호;김회철
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2005년도 제36회 하계학술대회 논문집 A
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    • pp.795-797
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    • 2005
  • This paper describes a measurement & verification scheme for the high efferent lighting program in Demand Side Management (DSM), which was Introduced in the beginning of the 1980's in Korea With the dramatic changes in the circumstance of power industry in Korea. It is required the reviewing for the existing process of DSM programs and the development of the new process methods/standards on the evaluation of DSM programs. To design an accurate evaluation scheme for the high efficient lighting program. In this paper, we develop an evaluation prototype for the high efficient lighting program using measurements and stipulated factors. The proposed scheme is tested by practical measurements and modified stipulated factors Results from the case studios show the proposed scheme could provide the practical performance evaluation results with promising accuracy.

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열차제어시스템의 안전계획 수립에 관한 연구 (A Study on the Safety Plan for a Train Control System)

  • 김종기;신덕호;이기서
    • 한국철도학회논문집
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    • 제9권3호
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    • pp.264-270
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    • 2006
  • In this paper we present a safety plan to be applied to the development of the TCS(Train Control System). The safety plan that can be applied to the life cycle of a system, from the conceptual design to the dismantlement, shows the whole process of the paper work in detail through the establishment of a goal, analysis and assessment, the verification. In this paper we study about the making a plan, the preliminary hazard analysis, the hazard identification and analysis to guarantee the safety of the TCS. The process far the verification of the system safety is divided into several steps based on the target system and the approaching method. The guarantee of the system safety and the improvement of the system reliability is fellowed by the recommendation of the international standards.

ECDSA를 사용한 Pedigree 디지털 서명의 설계 및 구현 (Design and Implementation of Digital Signature on Pedigree Using ECDSA)

  • 코시아완 요하네스;권준호;홍봉희
    • 한국정보과학회:학술대회논문집
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    • 한국정보과학회 2012년도 한국컴퓨터종합학술대회논문집 Vol.39 No.1(C)
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    • pp.286-288
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    • 2012
  • Facing the counterfeiting acts towards various products, many manufacturers implement ePedigree system to secure their supply chain. Using ePedigree, a distribution history including a valid product identifier from the manufacturer until the final retailer is recorded. And this ePedigree is signed by each involved supply chain party using digital signature. With this digital signature, any unauthorized alteration to the ePedigree document would generate a failed verification process. If there is a counterfeit product using a fake ePedigree document, it wouldn't be able to pass the verification process either. Hence, there wouldn't be any counterfeit product that could enter the legal supply chain and bought by the consumer. We are proposing to use ECDSA instead of RSA since it has faster performance and shorter key size. At a certain same security level, ECDSA only needs 163 bits, while RSA needs 1024 bits.

도시형자기부상열차 열차제어시스템 RAMS 적용에 관한 연구 (A Study on the Application of RAMS for Urban Maglev Signalling System)

  • 윤학선;이기서;이종우;박재영
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2008년도 추계학술대회 논문집
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    • pp.1113-1125
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    • 2008
  • In this paper we present a RAMS to be applied to the development of the Urban Maglev Train Signalling System. The RAMS that can be applied to the life cycle of a Signalling system, from the basic design to the dismantlement, shows the whole process of the paper work in detail through the establishment of a goal, analysis and assessment, the verification. In this paper we study about the making a plan, the preliminary hazard analysis, the hazard identification and analysis to guarantee the safety of the Signalling System. The process for the verification of the system safety is divided into several steps based on the target system and the approaching method. The guarantee of the system safety and the improvement of the system reliability is followed by the recommendation of the international standards.

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Leadframe Feeder Heat Rail의 설계와 검증 (Leadframe Feeder Heat Rail Design and Verification)

  • 김원종;황은하
    • 한국산업융합학회 논문집
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    • 제15권1호
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    • pp.37-42
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    • 2012
  • Trends in semiconductor equipment industry are to reduce the cost of producing semiconductor, semiconductor process development, facility development, and the minimum investment in terms of cost and quality. Semiconductor equipments are being considered to review and development is proceeding at the same time. In the first part of the semiconductor assembly process, in which the importance of die bonding process is emerging, a wide leadframe type die bonding machine is demanded for productivity. Die bonding machine was designed through experiments and by trial and error. It costs a lot of time and financial burden. The purpose of this study is to solve these problems by using the CAE tool 3G. By using finite element method, thermal analysis of die bonding machine to the various widths leadframe die bonder machine rail is performed for design.

EN 규격에 준한 용접대차프레임의 내구성 평가 (Durability Evaluation of Welding Bogie Frame in Compliance with EN Standard)

  • 김철수;강주석;안승호;정광우;전영석;박춘수;김재홍
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2008년도 춘계학술대회 논문집
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    • pp.2230-2235
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    • 2008
  • As a consequence of the standardization process developing in Europe, on April 2005 the new European standard EN 13749 was issued by the European standardization body CEN. The norm EN 13749 standardizes and develops the requirements already present in UIC leaflets for test verifications and define all technical requirements for the acceptance process in order to achieve a complete satisfactory design of the bogie. The aim of the norm is to define the complete design process of new railway bogies. It includes design procedures, assessment methods, verification and manufacturing quality requirements. In this study, fatigue analysis of the bogie frame is investigated comparing different approaches between conventional methodology and simulation results based on the VPD(Virtual Product Development).

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FPGA 컴파일 회피에 의한 효과적인 시뮬레이션 가속 (Efficient Simulation Acceleration by FPGA Compilation Avoidance)

  • 심규호;박창호;양세양
    • 정보처리학회논문지A
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    • 제14A권3호
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    • pp.141-146
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    • 2007
  • 본 논문에서는 FPCA 기반의 시뮬레이션가속을 통한 함수적 검증에서 매 설계오류의 수정 과정에서 필수적으로 진행되어야 하였던 긴 FPGA 컴파일 시간에 의한 오랜 디버깅턴어라운드시간을 단축할 수 있는 FPGA 컴파일 회피를 통한 효과적인 시뮬레이션가속 방법을 제시하였다. 마이크로컨트롤러 설계의 함수적 검증에 제안된 방법을 적용한 결과, 본 논문에서 제안된 방법이 시뮬레이션가속의 높은 시뮬레이션 수행 속도를 유지하는 동시에 디버깅턴어라운드시간도 크게 단축할 수 있음을 확인할 수 있었다.

전투기급 비행제어법칙 상사성 및 HILS 환경 신뢰성 검증 (Verification of Flight Control Law Similarity and HILS Environment Reliability for Fighter Aircraft)

  • 안성준;김종섭;조인제;이은용
    • 한국항공우주학회지
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    • 제37권7호
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    • pp.701-708
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    • 2009
  • 개발된 비행제어컴퓨터(DFLCC: Developed Flight Control Computer)의 비행제어법칙은 고등훈련기급 항공기의 시제 최종 형상의 비행제어소프트웨어(OFP: Operation Flight Program)를 기반으로 개발되었다. 비행제어법칙은 상용 개발 툴을 이용하여 GUI(Graphic User Interface) 환경에서 설계되며, C 코드로 변환되어 OFP 에 반영된다. 그리고 OFP는 정형화된 검증절차를 통하여 검증되는데, 검증과정을 거치기 전에 비실시간 환경에서 C코드로 변환된 비행제어법칙과 기반이 되는 비행제어법칙의 상사성(similarity)을 검증하고, 구성된 HILS(Hardware In-the-Loop Simulator) 환경의 신뢰성(reliability)을 사전에 검증하는 절차가 필요하다. 비행제어법칙의 상사성은 비실시간 환경에서 고등훈련기급 항공기의 시제 최종 버전의 비행제어법칙과 개발된 비행제어법칙의 응답특성을 상호 비교하여 검증된다. 또한, 구성된 HILS 환경의 신뢰성은 비실시간 시뮬레이션 툴을 기반으로 HILS 결과와 항공기 응답특성을 비교하여 검증된다. 본 논문에서는 항공기 응답을 직접 비교함으로써 개발된 비행제어법칙의 상사성과 HILS 환경의 신뢰성을 검증하였다.

BIM 기반 건축설계 관리 지원을 위한 클라우드 컴퓨팅 서비스 기능 제안 (A Proposal of Features of Cloud Computing Service for BIM based Architectural Design Management)

  • 안민규;최종문;이재욱;윤수원
    • 한국BIM학회 논문집
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    • 제4권2호
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    • pp.17-24
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    • 2014
  • Recently, there have been various attempts for the adoption and spread of Building Information Modeling (BIM) in the construction industry. However, the spread of BIM has been less satisfied than expected, because of the insufficient, expensive hardware and software for the authoring, analysis and so forth. As a solution to resolve the obstacles, the applications of cloud computing technology to BIM have been introduced. Due to the vendor-dependent functions and lack of verification on the work process, the spread of cloud-based BIM has been limited in Korea. Therefore, this study proposes the functions of cloud computing services which can support BIM-based design processes through the review of practitioners, questionnaire survey and analysis of design process.

온 칩 셀 특성을 위한 위상 오차 축적 기법 (Phase Error Accumulation Methodology for On-chip Cell Characterization)

  • 강창수;임인호
    • 전자공학회논문지 IE
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    • 제48권2호
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    • pp.6-11
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    • 2011
  • 본 논문은 나노 구조에서 ASIC 표준 라이브러리 셀의 특성에 대하여 전파지연시간 측정의 새로운 설계 방법을 제시하였다. 라이브러리 셀((NOR, AND, XOR 등)에 대한 정확한 시간 정보를 제공함으로서 ASIC 설계 흐름 공정의 시간적 분석을 증진시킬 수 있다. 이러한 분석은 기술 공정에서 반도체 파운드리 팀에게 유용하게 사용할 수 있다. CMOS 소자의 전파지연시간과 SPICE 시뮬레이션 은 트랜지스터 파라미터의 정확도를 예측할 수 있다. 위상오차 축적방법 물리적 실험은 반도체 제조공정($0.11{\mu}m$, GL130SB)으로 실현하였다. 표준 셀 라이브러리에서 전파지연시간은 $10^{-12}$초 단위까지 정확성을 측정할 수 있었다. VLSI STPE를 위한 솔루션은 배치, 시뮬레이션, 그리고 검증에 사용할 수 있다.