• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.49-60
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• 2002

A systematic design approach for Power distribution network (PDN) is presented aiming at applications to DRAM module designs. Three main stages are comprised in this design approach: modeling and simulation of a PDN based on a two-dimensional transmission line structure employing a partial element equivalent circuit (PEEC); verification of the simulation results through comparison to measured values; and design space scanning with PDN parameters. Impedance characteristics for do-coupling capacitors are analyzed to devise an effective way to stabilize power and ground plane Performance within a target level of disturbances. Self-impedance and transfer-impedance are studied in terms of distance between circuit features and the size of do-coupling capacitors. A simple equation has been derived to find the do-coupling capacitance values yielding impedance lower than design target, and thereby reducing the overall computation time. The effectiveness of the design methodology has been demonstrated using a DRAM module with discrete do-coupling capacitors and a strip structure.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.38-48
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• 1992

OEIC(Optoelectronic Integrated Circuit)'s can be integrated horizontally or vertically. Horizontal integration approach is, however, more immune to parasitic and more universally applicable. In this paper, a structural modeling, fabrication and characterization of PIN photodiodes which can be used in the horizontal integration are performed. For device modeling, we build a transmission line model from 2-D device simulation, from which lumped model parameters are extracted. The speed limits of the PIN photodiodes can also be calculated under various structural conditions from the model. Thus optimum design of horizontally integrated PIN photodiodes for high speed operation are possible. Such InGaAs/InP PIN photodiodes for long-wavelength communications are fabricated using pit etch, epi growth, planarization, diffusion and metallization processes. Planarization process using both RIE and wet etching and diffusion process using evaporated Zn$_{3}P_{2}$ film are developed. Characterization of the fabricated devices is performed through C-V and I-V measurements. At a reserve bias of 10V, the dark current is less than 5nA and capacitance is about 0.4pF. The calculated bandwidth using the measured series resistance and capacitance is about 4.23GHz.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.4
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• pp.412-418
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• 2012

Eddy current brakes are electromechanical devices used as variable mechanical loads for testing electrical machines. Accurate modeling of eddy current loss is an important t factor for optimum design of eddy brake systems. In this second part, we propose novel formulations of eddy current loss in novel claw-pole eddy brake system. The proposed model for eddy current loss in novel claw-pole eddy brake system depends on the size of the claw poles. Also, in this paper, the flux density is measured by using the magnetic circuit of the novel claw pole. The model results are compared with experimental results and they are found to be in good agreement.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.336-344
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• 2017

This paper presents the three-port DC-DC converter modeling and controller design procedure, which is part of the solid-state transformer (SST) to interface medium voltage AC grid to bipolar DC distribution network. Due to the high primary side DC link voltage, the proposed converter employs the three-level neutral point clamped (NPC) topology at the primary side and 2-two level half bridge circuits for each DC distribution network. For the proposed converter particular structure, this paper conducts modeling the three winding transformer and the power transfer between each port. A decoupling method is adopted to simplify the power transfer model. The voltage controller design procedure is presented. In addition, the output current sharing controller is employed for current balancing between the parallel-connected secondary output ports. The proposed circuit and controller performance are verified by experimental results using a 30 kW prototype SST system.

• Journal of the Korea Computer Industry Society
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• v.2 no.12
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• pp.1533-1540
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• 2001

In this paper, we described extraction method of electrical parameters and modeling method of PCB nets on PCB design process. To analyze electrical characteristics of real PCB structure, we selected a cache memory system as an experimental board and designed 6 layer PCB substrate. For extraction of the electrical parameters, we divided circuit elements into the components of conductor types which are wires, via holes, BGA balls etc. and combined the calculated value by real net structure to modeling the PCB nets. We analyzed the electrical characteristics of the PCB nets with the simulation tools of SPICE and XNS. The simulation analysis has shown that the maximum signal delay was 2.6ns and the maximum crosstalk noise was 281 mV and we found that the designed substrate was adequate to system specification.

• Nuclear Engineering and Technology
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• v.48 no.4
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• pp.1047-1057
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• 2016

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.31 no.2 s.257
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• pp.141-150
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• 2007

This paper presents a lumped model to predict crosstalk characteristics of thermally driven inkjet print heads. Using the lumped R-C model, heating characteristics of the head are predicted to be in agreement with IR temperature measurements. The inter-channel crosstalk is simulated using the lumped R-L network. The values of viscous flow resistance, R and flow inertance, L of connecting channels are adjusted to accord with the 3-D numerical simulation results of three adjacent jets. The crosstalk behaviors of a back shooter head as well as a top shooter head have been investigated. Predictions of the proposed lumped model on the meniscus oscillations are consistent with numerical simulation results. Comparison of the lumped model with experimental results identifies that abnormal two-drop ejection phenomena are related to the increased meniscus oscillations because of the more severe crosstalk effects at higher printing speeds. The degree of crosstalk has been quantified using cross-correlations between neighboring channels and a critical channel dimension for acceptable crosstalk has been proposed and validated with the numerical simulations. Our model can be used as a design tool for a better design of thermal inkjet print heads to minimize crosstalk effects.

• Journal of Fashion Business
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• v.25 no.1
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• pp.51-64
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• 2021

The purpose of this study was to develop smart bags that combining fashion-specific trends and smart information technologies such as light-emitting diodes(LED) and optic fibers by grafting marquage techniques that have recently become popular as part of eco-fashion. We applied e-textiles by designing leather tote bags that could show off LED luminescence. A total of two tote bags, a white-colored peacock design and a black-colored paisley design, divided the LED's light-emitting method into two types, incremental lighting and random light-emission to suit each design, and the locations of the optical fibers were also reversed depending upon the design. The production of circuits for the LEDs and optical fibers was based on the design, and a flexible conductive fabric was laser-cut instead of wire line and attached to the circuit-line location. A separate connector was underwent three-dimensional(3D)-modeling and was connected to high-luminosity LEDs and optic fiber bundles. The optical fiber logo part expressed a subtle image using a white-colored LED, which did not offset the LED's sharp luminous effects, suggesting that using LEDs with fiber optics allowed for the expression of each in harmony without being heterogeneous. Overall, the LEDs and fiber optic fabric were well-harmonized in the fashion bag using marquage techniques, and there was no sense of it being a mechanical device. Also, the circuit part was made of conductive fabric, which is an e-textile product that feels the same as a thin, flexible fabric. The study confirmed that the bag was developed as a smart wearable product that could be used in everyday life.

• Journal of Sensor Science and Technology
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• v.22 no.5
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• pp.364-368
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• 2013

Vibrational energy harvester based on piezoelectricity has been expected to be the dominant energy harvesting technology due to the advantages of high conversion efficiency, light weight and small size, night operation, etc. Its commercialization is just around the corner but the integration with power management electronics should be solved in advance. In this paper, therefore, fully-integrated design environment for piezoelectric energy harvesting systems is presented to assist co-design with the power management electronics. The proposed design environment is capable of analyzing the energy harvester including the package-induced damping effects and simulating the device and its power management electronics simultaneously. When the developed design environment was applied to the fabricated device, the simulated resonant frequency matched well with the experimental result with a difference of 2.97% only. Also, the complex transient response was completed in short simulation time of 3,001 seconds including the displacement distribution over the device geometry. Furthermore, a full-bridge power management circuit was modeled and simulated with the energy harvester simultaneously. Therefore the proposed, fully-integrated design environment is accurate and fast enough for the contribution on successful commercialization of piezoelectric energy harvester.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2006.05a
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• pp.153-156
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• 2006

The vibration isolation system is a system that attenuates the vibration transmitted from surroundings by using external energy supply like electricity and feedback and/or feedforward functions. Such a system needs stiff structure to make precise positioning without ripple within a certain bandwidth. So, a horizontal and rotary arrangement of the actuation module is suggested by using lever linkage. Modeling and kinematic formulation are completed and system identification is accomplished to tune the design variables accurately. The vibration isolation control is performed by mu-synthesis with the uncertainties in design variables. Low frequency signal enhancement circuit and saturation proof integration algorithm are devised to use seismic sensors for displacement control. This overall system shows good disturbance rejection performance.