• Journal of information and communication convergence engineering
• /
• v.8 no.1
• /
• pp.71-76
• /
• 2010

Scalable video coding (SVC) has been standardized as an extension of the H.264/AVC standard. SVC allows straightforward adaptation of video streams by providing layered bit streams. In this paper, we propose a SVC video-based multicasting system preserving scalable security which is able to provide a SVC video service while maintaining information security. In order to maintain information security between a server and a client during all transmission time, the proposed system immediately performs a packet filtering process without decoding with respect to encrypted data received in a routing device, thereby reducing an amount of calculations and latency.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.4
• /
• pp.488-496
• /
• 2016

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

• Journal of information and communication convergence engineering
• /
• v.11 no.2
• /
• pp.118-123
• /
• 2013

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.6
• /
• pp.1104-1114
• /
• 2007

Digital video compression technique has played an important role that enables efficient transmission and storage of multimedia data where bandwidth and storage space are limited. The new video coding standard, H.264/AVC, developed by Joint Video Team(JVT) significantly outperforms previous standards in compression performance. Especially, variable length code(VLC) plays a crucial pun in video and image compression applications. H.264/AVC standard adopted Context-based Adaptive Variable Length Coding(CAVLC) as the entropy coding method. CAVLC of H.264/AVC requires a large number of the memory accesses. This is a serious problem for applications such as DMB and video phone service because of the considerable amount of power that is consumed in accessing the memory. In order to overcome this problem in this paper, we propose a variable length technique that implements memory-free coeff_token, level, and run_before decoding based on arithmetic operations and using only 70% of the required memory at total_zero variable length decoding.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.46 no.3
• /
• pp.37-43
• /
• 2009

The new still image compression standard JPEG2000 is consisted of DWT and EBCOT. In this paper, proposed and designed new algorithm in efficient EBCOT. BPC based on the contort. Proposed BPC Algorithm is forecasted coding pass using Sigstage, column, mpass value. BAC design apply 4-pipeline stage. EBCOT designed using Verilog HDL. Verification and Synthesis using Xillinx FPGA technology.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.1029-1030
• /
• 2008

The Scalable Video Coding(SVC) extention of H.264/AVC standard. SVC based temporal, spatial, snd qualty scalability of video bit streams. In this paper, we will develop C-model program and hardware circuits for the chip design of the SVC decoder. In order to acquire the flexibility of the circuit design and reliability of the hardware system development. In these development, we utilize the results of the C-model program to achieve the independencies of each sub-blocks and check the efficiencies of the circuit design results.

• CDE review
• /
• v.3 no.3
• /
• pp.36-45
• /
• 1997

This paper presents the research on the development of Generic modeling system as a 3D CAD customizing system for the elevator design. This system enables to create a generic model which gives birth to many models. The generic model is expressed as a non-scale model or a standard model in this paper. Using the parametric design techniques, all their relationships are explicitly represented in the tables, not represented in implicit embedded coding. Owing to this method, designers can easily extend the generic model to contain more model families. All parametric relations are stored in relational database. A designer can retrieve various models from a generic model automatically, by using some key input values.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.7
• /
• pp.52-60
• /
• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.9 no.1
• /
• pp.122-130
• /
• 2001

In order to improve the efficiency of the design process and the quality of the resulting design, this study proposes a design method for determining design variables of an automotive wheel-bearing unit of double-row angular-contact ball bearing type by using a genetic algorithm. The desired performance of the wheel-bearing unit is to maximize system life while satisfying geometrical and operational constraints without enlarging mounting spae. The use of gradient-based optimization methods for the design of the unit is restricted because this design problem is characterized by the presence of discrete design variables such as the number of balls and standard ball diameter. Therefore, the design problem of rolling element bearings is a constrained discrete optimization problem. A genetic algorithm using real coding and dynamic mutation rate is used to efficiently find the optimum discrete design values. To effectively deal with the design constraints, a ranking method is suggested for constructing a fitness function in the genetic algorithm. A computer program is developed and applied to the design of a real wheel-bearing unit model to evaluate the proposed design method. Optimum design results demonstrate the effectiveness of the design method suggested in this study by showing that the system life of an optimally designed wheel-bearing unit is enhanced in comparison with that of the current design without any constraint violations.

• Proceedings of the Korea Inteligent Information System Society Conference
• /
• 2001.01a
• /
• pp.211-218
• /
• 2001

This paper introduces a method of constructing expert systems in an integrated environment for automatic software design. This integrated environment may be applicable from top-level system architecture design, data flow diagram design down to flow chart and coding. The system is integrated with three CASE tools, FSD (Functional Structure Diagram), DFD (Data Flow Diagram) and structured chart PAD (Problem Analysis Diagram), and respective expert systems with automatic design capability by reusing past design. The construction way of these expert systems is based on systematic acquisition of design knowledge stemmed from a systematic design work process of well-matured developers. The design knowledge is automatically acquired from respective documents and stored in the respective knowledge bases. By reusing it, a similar software system may be designed automatically. In order to develop these expert systems in a short period, these design knowledge is expressed by the unified frame structure, functions of th expert system units are partitioned mono-functions and then standardized components. As a result, the design cost of an expert system can be reduced to standard work procedures. Another feature of this paper is to introduce the integrated environment for automatic software design. This system features an essentially zero start-up cost for automatic design resulting in substantial saving of design man-hours in the resulting in substantial saving of design man-hours in the design life cycle, and the expected increase in software productivity after enough design experiences are accumulated.