• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1988년도 추계학술대회 논문집
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• pp.1-4
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• 1988

The high frequency and quasi-state C-V curves were measured to determine the interface state density in MNOS devices. Berglund method was appropriate for determination of energy distribution of interface state density all over the energy gap. Applying Vg vs Øs relation by Berlund method to comparison-analysis method of the high-frequency and quasi-static C-V curves, we were able to determine the energy distribution by only measured C-V curves without theoretical C-V curves. The interface state density near the conduction band was high at lower temperature than room temperature.

• 대한기계학회논문집
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• 제19권4호
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• pp.1095-1101
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• 1995

Numerical analysis of vertical solidification process allowing solid-liquid density change is performed by a hybrid method between a winite volume method (FVM) and a finite element method (FEM). The investigation focuses on the influence of solid-liquid density change and cooling rates on the motion of solid-liquid interface, solidified mass fraction, temperatures and thermal stresses in the solid region. Due to the density change of pure aluminium, solid-liquid interface moves more slowly but the solidified mass fraction is larger. The cooling rate of the wall is shown to have a significant influence on the phase change heat transfer and thermal stresses, while the density change has a small influence on the motion of the interface, solidified mass fraction, temperature distributions and thermal stresses. As the cooling rate increases, the thermal stresses become higher at the early stage of a solidification process, but it has small influence on the final stresses as the steady state is reached.

• Bulletin of the Korean Chemical Society
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• 제31권3호
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• pp.753-756
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• 2010

• 센서학회지
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• 제31권4호
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.465-468
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• 1987

This paper describes a model to calculate the equilibrium electron density of MODFET at the interface that takes into account the simultaneous shallow and deep level in the Al-GaAs layer. In the present study we have made an investigation of the interface electron density with different values of the AlGaAs doping density and spacer layer thickness, considering simultaneously two doner levels. In this case, the ratio of the shallow to the deep donor concentraction is considered. From the comparison with early experimental results we could find the deep level and that the deep donor concentration is about 50% with the Al mole fraction X ${\sim}0.3$, activation energy Edx=65meV, temperature $77^{\circ}K$ and spacer thickness range $50A{\sim}100A$. Also we have investigated the effect of the temperature. As temperature increase, at critical mole fraction X the nature of the donor concentration changes from $\Gamma$ to L and X.

• 전기전자학회논문지
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• 제18권4호
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• pp.447-455
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• 2014

본 연구에서는 4H-SiC MOSFET의 주요 문제점인 $SiC/SiO_2$ 계면의 특성을 향상시키기 위해 PECVD (plasma enhanced chemical vapor deposition) 공정을 이용하여 n-based 4H-SiC MOS Capacitor를 제작하였다. 건식 산화 공정의 낮은 성장속도, 높은 계면포획 밀도와 $SiO_2$의 낮은 항복전계 등의 문제를 극복하기 위하여 PECVD와 NO어닐링 공정을 사용하여 MOS Capacitor를 제작하였다. 제작이 끝난 후, MOS Capacitor의 계면특성을 hi-lo C-V 측정, I-V 측정 및 SIMS를 이용해 측정하고 평가하였다. 계면의 특성을 건식 산화의 경우와 비교한 결과 20% 감소한 평탄대 전압 변화, 25% 감소한 $SiO_2$ 유효 전하 밀도, 8MV/cm의 증가한 $SiO_2$ 항복전계 및 1.57eV의 유효 에너지 장벽 높이, 전도대 아래로 0.375~0.495eV만큼 떨어져 있는 에너지 영역에서 69.05% 감소한 계면 포획 농도를 확인함으로써 향상된 계면 및 산화막 특성을 얻을 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
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• pp.189-192
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• 1988

Nitrided oxides have been investigated recently for application as a replacement for thermally grown $SiO_2$ in MIS devices. In this paper, thin oxides were nitrided in $N_2$ Plasma ambient. With the measurement of the equivalent paralled conductance and capacitance by the using coductance technique, the characterization of Si-SiON interface is developed. The interface state density of Si-SiON is obtained by $1{\times}10^{11}{\sim}9{\times}10^{11}(eV^{-1}Cm^{-2})$. After${\pm}$B-T stress is performed on the sample, the interface state density gets increased.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.143.1-143.1
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• 2016

Ge is a promising candidate to replace Si in MOSFET because of its superior carrier mobility, particular that of the hole. However Ge oxide is thermodynamically unstable. At elevated temperature, GeO is formed at the interface of Ge and GeO2, and its formation increases the interface defect density, degrading its device performance. In search for a method to surmount the problem, we investigated Ge oxidation through an inert capped oxide layer. For this work, we prepared low doped n-type Ge(100) wafer by removing native oxide and depositing a capping layer, and show that GeO2 interface can be successfully grown through the capping layer by thermal oxidation in a furnace. The thickness and quality of thus grown GeO2 interface was examined by ellipsometry, XPS, and AFM, along with I-V and C-V measurements performed at 100K to 300K. We will present the result of our investigation, and provide the discussion on the oxide growth rate, interface state density and electrical characteristics in comparison with other studies using the direct oxidation method.

• 한국재료학회지
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• 제18권9호
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• pp.482-485
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• 2008

Tetragonal-$Ni_{1-x}Pd_x$Si/Si (001) structure was studied by using density functional theory (DFT). An epitaxial interface between $2{\times}2{\times}4$ (001) tetragonal-NiSi supercell and $1{\times}1{\times}2$ (001) Si supercell was first constructed by adjusting the lattice parameters of B2-NiSi structure to match those of the Si structure. We chose Ni atoms as a terminating layer of the B2-NiSi; the equilibrium gap between the tetragonal-NiSi and Si was calculated to be 1.1 ${\AA}$. The Ni atoms in the structure moved away from the original positions along the z-direction in a systematic way during the energy minimization. Two different Ni sites were identified at the interface and the bulk, respectively. The two Ni sites at the interface have 6 and 7 coordination numbers. The Ni sites with coordination number 6 at the interface were located farther away from the interface, and were more favorable for Pd substitution.

• 대한기계학회논문집A
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• 제21권3호
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• pp.414-422
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• 1997

The characteristics on the extension of the CED(Crack Energy Density) concept to the interface kinked crack problems in a dissimilar are examined. Each mode contributions of CED are found by symmetric and antisymmetric conponents and domain independent integrals. Finite element calculation is carried out to simulate the interface kinked crack growth on a bimaterial. The focus is the establishment of fracture criterion with CED and finding the orientation of crack extension. From the results, a prediction about the extension behavior of an interface kinked crack can be done. And we show that CED can be a parameter to indicate fracture criterion at an interface kinked crack.