• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8A
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• pp.950-961
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• 2004

In this paper, we measured and analyzed propagation characteristics in a subway tunnel that is recently increasingly becoming one of the radio communication environments. The measurements are carried out in a subway tunnel with frequency bands of 2.45㎓ and 5.8㎓. The length of tunnel we used for this study is 175m of LOS (Line-of-sight) and 270m of NLOS (Non Line-of-Sight). The subway tunnel is curved and its cross section is horseshoe type. The measurement systems we employ in this study are a narrow-band system and a wide-band system. The narrow-band system is used to get path loss measurement and the wide-band system is used to figure out delay profile measurement. In particular, the wide-band system consists of 1023 length PN sequence generator using a chip rate of 80MHz based on a sliding correlation technique. The omni-directional antennas and directional antennas are used to analyze propagation characteristics for beam type of antenna. The path loss displays only pure path loss of a tunnel environment. The delay profile indicates the mean excess delay and RMS (root mean square) delay spread.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.2
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• pp.75-82
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• 2000

In this Paper, a new type of feedforward linearizer using a delay line which controls the phase characteristics of the correction amplifier block is proposed. The extra delay line provides the control-ability of IM signals so that the IM rejection is accomplished without the conventional pilot tone. The error signal loop consists of several key components such as phase shifter and attenuator, subtractor. These key components are replaced by new designs in order to obtain better linearization characteristics without the pilot tone generator which is indispensable in the conventional linearizer designs. The proposed linearizer was designed at Korean PCS band and combined with 35W HPA manufactured by KMW inc., and tested with two-tone signals separated 0.6MHz apart at the center frequency of 1855MHz. The experimental results show C/l improvement by 16.9 ~ 24.6 dB over 15 dB dynamic range(30 ~45 dBm) which gave IMD of 58.5~63.2 dBc for the designed LPA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1552-1558
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• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Korean Journal of Optics and Photonics
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• v.16 no.6
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• pp.547-552
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• 2005

We have fabricated and characterized optical delay lines for optical coherence tomography, which is composed of cylindrical PZT(piezoelectric transducer) and single mode optical fiber. The polarization mode dispersion from the optical delay lines was compensated by the polarization controllers. By applying the duplex optical delay line, we minimized the thermal drift due to optical delay lines and obtained the scan range of 2 times that of a single optical delay line. The OCT system showed resolution of $18.6\pm0.5{\mu}m$, scanning range of 1.68mm, and scanning speed of 360.4mm/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.5B
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• pp.365-369
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• 2012

It is very important to control synchronization by inter-network delay compensation in high speed synchronous optcial transmission network systems. In this study we designed a delay measurement system based on OTDR using Rayleigh backscatterer in order to compensate for time delay due to the length of optical fiber line. We observed waveform variations on both averaging time and peak power of laser pulse. Finally, we executed experimental demonstration on its accuracy and test repeatability by comparison to the methods practically used in the industry. Experimental results show maximum error of 0.06usec and standard deviation of 0.021usec, which means it's possibly applied to delay control system for mobile repeaters and stations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.1-8
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• 2000

In this paper, the dependence of interconnect line-induced delay time on the size of CMOSFET gate width is characterized. In case of capacitance dominant interconnect line, the total delay time decreases as transistor size increases. However, there exists a transistor size for minimum total delay time when both of resistance and capacitance of interconnect line become larger than those of transistor. The optimum transistor size for minimum total delay time is obtained using an analytic equation and the experimental results showed good agreement with the calculation.

• Journal of electromagnetic engineering and science
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• v.3 no.1
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• pp.62-66
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• 2003

Novel coupled line phase shifters and its equivalent phase delay line for compact broadband phased array antennas are proposed. These phase control circuits are designed to be less complex, small size and to use a less number of active devices. The phase shifter is able to control a 120$^{\circ}$ phase shift continuously, and the phase delay line for a reference phase has a fixed 60$^{\circ}$ shifted phase. Both have the low phase error of less than $\pm$3.5$^{\circ}$ and the low gain variations of less than 1 ㏈ within the 300 MHz bandwidth. These proposed circuits are adequate to form the efficient beam-forming networks with compactness, broadband, less complexity, and low cost.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.21-29
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• 2002

This paper describes a high resolution DLL(Delay Locked Loop) using all digital circuits. The proposed architecture is based on the three stage of coarse, fine and ultra fine phase tuning block which has a phase detector, selection block and delay line respectively. The first stage, the ultra fine phase tuning block, is tune to accomplish high resolution using a vernier delay line. The second and third stage, the coarse and fine tuning block, are tuning the phase margin of Unit Delay using the delay line and are similar to each other. It was simulated in 0.35um CMOS technology under 3.3V supply using HSPICE simulator. The simulation result shows the phase resolution can be down to lops with the operating range of 250MHz to 800MHz.

• Journal of electromagnetic engineering and science
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• v.6 no.2
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• pp.110-116
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• 2006

A reflective array type surface acoustic wave(SAW) dispersive delay line(DDL) with high time-bandwidth at the V/UHF-band is designed and fabricated for compressive receiver applications. This type of the SAW DDL has the properties of the relative bandwidth of 20 %, the time delay of 49.89 usec, the insertion loss of 38.5 dB and the side lobe rejection of 39 dB. In comparison with a commercial SAW DDL, the insertion loss, amplitude ripple and side lobe rejection are improved by $1.5dB{\pm}0.6dB$ and 4 dB respectively. Using the fabricated SAW DDL, the prototype of the compressive receiver is developed. It is composed of RF converter, fast tunable LO, chirp LO, A/D converter, signal processing unit and control unit. This prototype system shows a fine frequency resolution of below 30 kHz with high scan rate.