• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.136-141
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• 2007

The frequency accuracy and phase alignment is necessary for ensuring the quality of service (QoS) for applications such as voice, real-time video, wireless hand-off, and data over a converged access medium at the telecom network. As telecom networks evolve from circuit to packet switching, proper synchronization algorithm should be meditated for IP networks to achieve performance quality comparable to that of legacy circuit-switched networks. The Time of Packet (ToP) specified in IEEE 1588 is able to synchronize distributed clocks with an accuracy of less than one microsecond in packet networks. But, The ToP can be affected by impairments of a network such as packet delay variation. This paper proposes the efficient method to minimize the expectable delay variation when ToP synchronizes the distributed clocks. The simulation results are presented to demonstrate the improved performance case when the efficient ToP transmit algorithm is applied.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.4
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• pp.170-178
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• 2001

Deadbeat technique has been proposed as a digital controller for an UPS inverter to achieve the fast, response to a load variation and to conserve a very low THD under a nonlinear load condition. This scheme contains a fatal drawback, sensitivity against parameter variation and calculation time delay. This paper proposes a second order deadbeat controller, which fundamentally solves the calculation time delay problem and certainly guarantees the robustness of the parameter's variation. RLP(Repetitive Load Predictor) which predicts the load current ahead of two sampling time and FVR(Fundamental Voltage Regulator) which eliminates the fundamental errors of the output voltage are also proposed for the second order deadbeat controller to apply to UPS inverter systems. These are shown theoretically and practically through simulation and experiment.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1056-1058
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• 2000

Deadbeat technique has been proposed as a digital controller for an UPS inverter to achieve the fast response to a load variation and to conserve a very low THD under a nonlinear load condition. This scheme contains a fatal drawback, sensitivity against parameter variation and calculation time delay. This paper proposes a second order deadbeat current controller, which fundamentally solves the calculation time delay problem and certainly guarantees the robustness of the parameter's variation. This is shown theoretically and practically through simulation and experiment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• ETRI Journal
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• v.32 no.6
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• pp.854-862
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• 2010

One-way delay variation (OWDV) has become increasingly of interest to researchers as a way to evaluate network state and service quality, especially for real-time and streaming services such as voice-over-Internet-protocol (VoIP) and video. Many schemes for OWDV measurement require clock synchronization through the global-positioning system (GPS) or network time protocol. In clock-synchronized approaches, the accuracy of OWDV measurement depends on the accuracy of the clock synchronization. GPS provides highly accurate clock synchronization. However, the deployment of GPS on legacy network equipment might be slow and costly. This paper proposes a method for measuring OWDV that dispenses with clock synchronization. The clock synchronization problem is mainly caused by clock skew. The proposed approach is based on the measurement of inter-packet delay and accumulated OWDV. This paper shows the performance of the proposed scheme via simulations and through experiments in a VoIP network. The presented simulation and measurement results indicate that clock skew can be efficiently measured and removed and that OWDV can be measured without requiring clock synchronization.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.103-106
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• 2010

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1376-1385
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• 2000

The phase characteristic of delay line in feedfarward linearizer has been changed due to variation of operating temperature. In this paper, design method of fixed phase control circuit of group delay line using adaptive vector control is derived. To maintain transfer characteristics of nominal operating temperature, the error correlated signals, which are changed adaptively due to changing of temperature, are added to main signals. The proposed method maintains transfer characteristics under 0.06dB of insertion loss and 0.36$^{\circ}$ of phase variation in case of 1-tone(880 MHz) and under 0.07 dB of insertion loss and 0.35$^{\circ}$ of phase variation in case of 2-tones(877 MHz, 882 MHz) for 10dB input power dynamic range and +/-10$^{\circ}$ phase variation respectively.

• Journal of Advanced Navigation Technology
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• v.23 no.5
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• pp.386-391
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• 2019

This paper presents analysis results for the effect of the directional group delay of the antenna to implement a precision radio navigation system. The analysis was conducted through antenna simulation and test, and the test was performed in an anechoic chamber. The directional group delay of the antenna was calculated in phase-based analysis method. The results showed that a variation of up to 7.7ns in group delay occurred per antenna direction. The group delay variation from the analysis is 2.31 meters when converted into distance. It was tested using a real radio navigation system based on the time of arrival (TOA). The test verified the distance variation of 2.1 meters, and this value is similar to those obtained from the simulation and chamber test analysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.199-207
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• 2001

We propose an adaptive shaping controller equipped with the technologies of shaping and buffering VoIP packets arriving at the receiving end by the CAM-type controller. In order to conceal interarrival packet delay variation, the conventional jitter buffers force them to be too large, thereby causing the audio quality to suffer excessive delay. However, by using our proposed method, the delay caused by shaping operation dynamically increases or decreases on the level of jitter that exists with in the IP network. This makes the delay accommodates adaptively the network jitter condition. The less jitter network has the fewer delay the shaping controller requires for jitter elimination. And the CAM-type method generally makes the shaping operation faster and leads to processing packets in as little time as can. We analyse the packet loss and delay performance dependency on the average talk ratio and the number of jitter buffer entries in shaping controller. Surprising, we show that the average delay using our shaping controller is about 70msec. This performance is much better than with the delay equalization method which forces the receiving end to delay about 60msec.