• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2007년도 학술대회
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• pp.136-141
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• 2007

The frequency accuracy and phase alignment is necessary for ensuring the quality of service (QoS) for applications such as voice, real-time video, wireless hand-off, and data over a converged access medium at the telecom network. As telecom networks evolve from circuit to packet switching, proper synchronization algorithm should be meditated for IP networks to achieve performance quality comparable to that of legacy circuit-switched networks. The Time of Packet (ToP) specified in IEEE 1588 is able to synchronize distributed clocks with an accuracy of less than one microsecond in packet networks. But, The ToP can be affected by impairments of a network such as packet delay variation. This paper proposes the efficient method to minimize the expectable delay variation when ToP synchronizes the distributed clocks. The simulation results are presented to demonstrate the improved performance case when the efficient ToP transmit algorithm is applied.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제50권4호
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• pp.170-178
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• 2001

Deadbeat technique has been proposed as a digital controller for an UPS inverter to achieve the fast, response to a load variation and to conserve a very low THD under a nonlinear load condition. This scheme contains a fatal drawback, sensitivity against parameter variation and calculation time delay. This paper proposes a second order deadbeat controller, which fundamentally solves the calculation time delay problem and certainly guarantees the robustness of the parameter's variation. RLP(Repetitive Load Predictor) which predicts the load current ahead of two sampling time and FVR(Fundamental Voltage Regulator) which eliminates the fundamental errors of the output voltage are also proposed for the second order deadbeat controller to apply to UPS inverter systems. These are shown theoretically and practically through simulation and experiment.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.1056-1058
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• 2000

Deadbeat technique has been proposed as a digital controller for an UPS inverter to achieve the fast response to a load variation and to conserve a very low THD under a nonlinear load condition. This scheme contains a fatal drawback, sensitivity against parameter variation and calculation time delay. This paper proposes a second order deadbeat current controller, which fundamentally solves the calculation time delay problem and certainly guarantees the robustness of the parameter's variation. This is shown theoretically and practically through simulation and experiment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• Journal of information and communication convergence engineering
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• 제8권4호
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• ETRI Journal
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• 제32권6호
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• pp.854-862
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• 2010

One-way delay variation (OWDV) has become increasingly of interest to researchers as a way to evaluate network state and service quality, especially for real-time and streaming services such as voice-over-Internet-protocol (VoIP) and video. Many schemes for OWDV measurement require clock synchronization through the global-positioning system (GPS) or network time protocol. In clock-synchronized approaches, the accuracy of OWDV measurement depends on the accuracy of the clock synchronization. GPS provides highly accurate clock synchronization. However, the deployment of GPS on legacy network equipment might be slow and costly. This paper proposes a method for measuring OWDV that dispenses with clock synchronization. The clock synchronization problem is mainly caused by clock skew. The proposed approach is based on the measurement of inter-packet delay and accumulated OWDV. This paper shows the performance of the proposed scheme via simulations and through experiments in a VoIP network. The presented simulation and measurement results indicate that clock skew can be efficiently measured and removed and that OWDV can be measured without requiring clock synchronization.

• Journal of information and communication convergence engineering
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• 제8권1호
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• pp.103-106
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• 2010

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

• 한국전자파학회논문지
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• 제11권8호
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• pp.1376-1385
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• 2000

본 논문은 Feedforward 선형화기에서 온도영향으루 인한 군속도 지연선로의 위상 변화를 벡터 결합이론을 이용하여 고정시키는 회로에 관한 것이다. 상온에서의 군속도 지연선로의 신호 전달특성이 항상 일정하게 유지되게 하기 위해, 온도에 따른 군속도 지연선로의 신호에 온도변화에 대해 자동 적응적으로 변하는 보정신호를 인가하여 온도변화에도 항상 일정한 신호특성을 얻도록 하였다. 이 전송선로에 10 ㏈의 동작신호 레벨 변화와 +/-$10^{\circ}$의 위상 변화에 대해 880 MHz 및 1-tone 신호는 0.06 ㏈의 삽입 손실 변화와 0.36$^{\circ}$의 위상이내에서 위상이 변했고, 877 MHz 및 882 MHz인 2-tone 신호에 대해 0.07 ㏈의 삽입손실변화와 0.35$^{\circ}$의 위상이내에서 위상이 변하는 특성을 얻었다.

• 한국항행학회논문지
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• 제23권5호
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• pp.386-391
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• 2019

본 논문은 정밀한 전파항법시스템 구현을 위해 안테나의 방향별 군지연 차이가 시스템에 미치는 영향을 분석하였다. 분석은 안테나 시뮬레이션과 시험을 통해서 수행 하였고, 시험은 무반향 챔버에서 진행 하였다. 안테나의 방향별 군지연은 위상(phase)을 기반으로 분석 하였으며, 측정 분석 결과 안테나의 방향별로 최대 약 7.7 ns까지 군지연 차이가 발생했다. 분석된 군지연 차이를 거리로 환산하면 약 2.31 m이며, 이를 실제 TOA (time of arrival)기반의 전파항법시스템에서 시험 하였다. 시험 결과 2.1 m의 거리 변화를 확인 하였으며, 이는 시뮬레이션과 챔버 시험 분석 값과 유사한 수치이다.

• 한국통신학회논문지
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• 제26권12C호
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• pp.199-207
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• 2001

이 논문에서는 수신측에 도달하는 VoIP 패킷들을 쉐이핑하고 또 버퍼링하기 위하여 CAM형의 제어기를 사용하는 기술로 적응식 쉐이핑 제어기를 제안한다. 패킷간 도탁 시간 간격의 변이를 없애기 위하여, 지연 균등화 방법에 입각한 전통적인 jitter buffer는 요구되는 버퍼크기가 너무 커지고 이에 기인한 지나친 지연으로 오디오 질이 나빠지는 원인이다. 그러나, 이 논문에서 제안한 방법을 사용하면, 도착시간 간격 변이를 없애기 위한 쉐이핑에 의해 야기된 지연은 동적으로 Ip 네크웍에서 존재하는jitter 수준의 정도에 따라 증가 또는 감소한다. 이것은 네트웍의 지연시간 변이 상황에 적응하여 동작하게 되는데, 네트웍에 지연시간 변이현상이 심하지 않으면 쉐이핑 제어기에서의 지연시간이 작아진다는 것을 의미한다. 또 CAM형으로 동작하기 때문에 쉐이핑 과정이 빨리 이루어지고 이는 수신측에서의 VoIP 패킷 처리 시간을 최대한 단축시켜 준다. 마지막으로 쉐이핑 제어기에서의 평균 TALKratio와 jitter buffer 엔트리 수에 대한 패킷 손실과 지연 성능이 관계를 분석한다. 놀랍게도, 제안한 쉐이핑 제어기를 사용할 때의 평균 지연이 약 10msec라는 것을 확인하였다. 이 성능은 수신측에서 60msec 강제지연을 강요하는 지연시간 균등화 방법보다 훨씬 더 좋은 성능을 보여주는 것이다.