• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.11
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• pp.924-933
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• 2013

In this paper, we propose a modeling of the broadcasting in the IEEE 802.11p MAC protocol for the VANET(Vehicular Ad hoc Networks). Due to the fact that the beacon message which is needed for the safety services is shared via broadcasting, the analytical modeling of the broadcasting is crucial for the optimum design of the services. Two characteristics specific to the IEEE 802.11p are reflected in the modeling; the time limited CCH interval caused by the channel switching between the CCH and SCH, and no retransmission of the broadcasted messages. In the proposal, we assumed no restriction on the moment of generation of the beacon messages. We allow the messages to be generated and broadcasted within the whole CCH interval. Simulation results prove the accuracy of the proposed modeling. Noticeable improvements are also observed in terms of the performance indices such as the successful delivery ratio, transmission delay, and the variation of the delay.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.19-27
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• 2016

Nowadays the adaptive buffering techniques for burst stream packet configuration and its operation algorithm to save energy in IP core network have been studied. This paper explains the selection method of packet buffering interval for energy saving when configuring burst stream packet at the ingress router in IP core network. Especially the adaptive buffering interval and its implementation scheme are required to improve the energy saving efficiency at the input part of the ingress router. In this paper, we propose the best adaptive buffering scheme that a current buffering interval is adaptively buffering scheme based on the input traffic of the past buffering interval, and analyze its characteristics of energy saving and end-to-end delay by computer simulation. We show the improvement of energy saving effect and reduction of mean delay variation when using an appropriate inverse-function selecting the buffering interval for the configuration of burst stream packet in this paper. We confirm this method have superior properties compared to other method. The proposed method shows that it is less sensitive to the various input traffic type of ingress router and a practical method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.397-400
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• 2018

This paper presents a miniaturized 65 nm CMOS 30~46 GHz wideband amplifier. To minimize the chip area, coupled inductors are used in the matching networks. The measurement shows that the fabricated amplifier exhibits 9.3 dB of peak gain, 16 GHz of 3 dB bandwidth, and 42 % fractional bandwidth. The measured input and output return losses were more than 10 dB at 35.8~46.0 GHz and 28.6~37.8 GHz, respectively. The chip consumes 42 mW at 1.2 V. The measured group delay variation is 19.1 ps within the 3 dB bandwidth and the chip size excluding the pads is $0.09mm^2$.

• Transactions of the Korean Society of Mechanical Engineers
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• v.15 no.2
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• pp.463-477
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• 1991

This study proposed a new method to design a robot manipulator control system capable of tracking the trajectories of joint angles in a reasonable accuracy to cover with actual situation of varying payload, uncertain parameters, and time delay. The direct adaptive model following control method has been used to improve existing industrial robot manipulator control system design. The proposed robot manipulator controller is operated by adjusting its gains based on the response of the manipulator in such a way that the manipulator closely matches the reference model trajectories predefined by the designer. The manipulator control system studied has two loops: they are an inner loop on adaptive model following controller to compensate nonlinearity in the manipulator dynamic equation and to decouple the coupling terms and an outer loop of state feedback controller with integral action to guarantee the stability of the adaptive scheme. This adaptation algorithm is based on the hyperstability approach with an improved Lyapunov function. The coupling among joints and the nonlinearity in the dynamic equation are explicitly considered. The designed manipulator controller shows good tracking performance in various cases, load variation, parameter uncertainties. and time delay. Since the proposed adaptive control method requires only a small number of parameters to be estimated, the controller has a relatively simple structure compared to the other adaptive manipulator controllers. Therefore, the method used is expected to be well suited for a high performance robot controller under practical operation environments.

• Journal of Broadcast Engineering
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• v.21 no.3
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• pp.349-356
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• 2016

In this paper, we propose an efficient assignment method that assigns quantization parameter (QP) in accordance with group of picture (GOP) structure given in HEVC encoder. Each video frames can have difference QP values based on given GOP configuration for HEVC encoding. Particularly, for important frames we can assign low QP values, and vice versa. However, there has not been thorough investigation on efficient QP assignment method by far. Even in HEVC reference software encoder, only monotonic QP assignment method is employed. Thus, the proposed method assign adaptive QP values to each GOP so that temporal dynamic activity between GOPs can be exploited. Through the experiment, the proposed method showed a 7.3% gain of compression performance in terms of BD-rate compared to HEVC test model (HM) in low-delay configuration, and outperformed the existing QP assignment study on average.

• Journal of Korea Multimedia Society
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• v.12 no.1
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• pp.69-84
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• 2009

In this paper, a real-time web-casting framework for many individuals or small organizations imploring internet broadcasting, is designed and implemented. It is the purpose of the proposed framework that any individual can easily construct his own broadcast station if he has minimum facility for the content transmission to the framework. This type of system should have a flexible architecture to be applicable in wide variation of operational environment. Since the proposed framework follows a component-based hierarchical structure consisting of 3 types of components, it can effectively cope with change of internal or external operational environment by simple modification of the associated component with the change. Also, various types of target application systems in the aspects of cost and performance can be constructed in accordance with how to associate upper layer components with hardware platforms. A real prototype system based on the proposed framework is implemented, and then the response delay time is measured under varying number of content productions and content receivers. The results show that the response delay time follows M/M/1 model, which is one of the well-known performance models, and the implemented system may accommodate from 16 to 20 productions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8C
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• pp.803-811
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• 2002

Asynchronous Transfer Mode-Passive Optical Network(ATM-PON) Technology is one of the best solutions for implementation of broadband access network. In this paper, we propose a new Dynamic Bandwidth Allocation (DBA) algorithm for ATM-PON systems. The DBA is a key technique for data traffic management. DBA has been studied widely to allow ATM-PON to transport data traffic cost-effectively and efficiently, and currently a hot standardization issue in Full Service Access Network(FSAN) and ITU-T. The proposed DBA algorithm efficiently manages the user traffics according to their service categories. Performance of the proposed algorithm, in aspect of Cell Transfer Delay(CTD) and Cell Delay Variation(CDV), is evaluated using computer simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.303-317
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• 2013

Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.17-22
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• 2010

We have proposed and experimentally demonstrated a novel fiber Bragg grating (FBG) sensing interrogation method using bidirectional modulation of a Mach-Zehnder electro-optical modulator (MZ-EOM). The proposed structure consists mainly of a broadband light source (BBS), FBG, MZ-EOM, chirped fiber Bragg grating (CFBG), and photodetector (PD). We have obtained the transfer functions of the proposed structure and calculated the time delay from the change in the free spectral range (FSR) for ten wavelengths over the frequency range of 505 MHz to 525 MHz. The results show that the time delay and the wavelength variation have a good linear relationship with a gradient of 12.9 ps/0.2 nm, which can be usefully applied to FBG strain or temperature sensors and other multiplexed sensor applications.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.