• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.8
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• pp.350-354
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• 2005

This paper proposes a new method for delay time calculation in RLC interconnects. This method is simple, but precise. The proposed method can calculate delay time of RLC interconnects by simple numerical formula calculation without complex moment calculation using reduced model in RLC interconnects. The results using the proposed method for RLC circuits show that average relative error is within $10\%$ in comparison with HSPICE simulation results.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.99-102
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• 2005

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard $0.25\;{\mu}m$ CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The $g_m$ value of MOSFET is calculated by using new drain current model.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.5
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• pp.193-193
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• 2003

This Paper analyses several model-order reduction methods and then proposes an improved n model and a new delay calculation method to be used in analyzing RC-class interconnects, which does not involve moment calculation processes. The proposed delay calculation method has been derived by combining the unproved $\pi$ model, the concept of effective capacitance and Elmore delay. This method has an advantage in that it can be applied in the calculation of end-to-end delay as well as incremental delay.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.5
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• pp.193-200
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• 2003

This Paper analyses several model-order reduction methods and then proposes an improved n model and a new delay calculation method to be used in analyzing RC-class interconnects, which does not involve moment calculation processes. The proposed delay calculation method has been derived by combining the unproved $\pi$ model, the concept of effective capacitance and Elmore delay. This method has an advantage in that it can be applied in the calculation of end-to-end delay as well as incremental delay.

• Journal of Korean Society of Transportation
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• v.13 no.1
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• pp.125-152
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• 1995

The purposes of this study are twofold ; (1) to investigate the accuracy of estimation power of the individual models. such as those of Highway Capacity Nanual (HCM), Korea Highway Capacity Manual (KHCM), and NationalCooperative Highway Research Program(NCHRP) Report339 ; and (2) to develop an adjusted delay model which can be applied to the signal control system in urban areas. The study is mainly focused on four subjects related to the research purposes, which are as follows ; (1) characteristecs of exsisting delay models ; (2) inherent problems in exsisting delay models : (3) validation of the proposed model by the comparison of observed delay with estimated delay :and (4) a method which can be applied to develop an appropriate delay model for actrual signal control systems by the adjusted fact of the proposed model.

• Proceedings of the KOSOMBE Conference
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• v.1997 no.05
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• pp.165-170
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• 1997

In this paper, we consider the aortic sinus baroreceptor, which is the most representative baroreceptors sensing the variance of pressure in the cardiovascular system(CVS), and propose heart activity control model to observe the effect of delay time in heart period and stroke volume under the regulation of baroreflex in arotic sinus. The proposed heart activity baroreflex regulation model contains CVS electric circuit sub-model, baroreflex regulation sub-model and time delay sub-model. In these models, applied electric circuit sub-model is researched by B.C.Choi and the baroreflex regulation sub-model transforms the input, the arotic pressure of CVS electric circuit sub-model, to outputs, heart period and stroke volume by mathematical nonlinear feedback. We constituted the time delay sub-model to observe sensitivity of heart activity baroreflex regulation model by using the variable value to represent the control signal transmission time from the output of baroreflex regulation model to efferent nerve through central nervous system. The simulation object of this model is to observe variability of the CVS by variable value in time delay sub-model. As simulation results, we observe three patterns of CVS variability by the time delay. First, if the time delay is over 2.5 sec, arotic pressure, stroke volume and heart rate is observed nonperiodically and irregularly. Second, if the time delay is from between 0.1 sec and 0.25 sec, the regular oscillation is observed. Finally, if time delay is under 0.1 sec, then heart rate and arotic pressure-heart rate trajectory is maintained in stable state.

• The Journal of the Acoustical Society of Korea
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• v.22 no.8
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• pp.680-686
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• 2003

Digital waveguide model is a general method that is used in physical modeling of musical instruments. Wave motion is analyzed by time or by space in digital waveguide model. Because sampling is made via time, it is general that musical instrument model is described by wave motion of time. In this paper, we synthesized the musical instrument sound by adding instrument body model to the spatial based string model. In this way, we could improve sound quality and process musical instrument model's tone control variables effectively. We explained about delay error that happens in string and body in space based sampling and showed method to process fractional delay using FD (Fractional Delay)filter. Finally, we explained the relation between tone quality and number of delays. And we also compared the result with time base digital waveguide model.

• Journal of Positioning, Navigation, and Timing
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• v.5 no.4
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• pp.213-219
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• 2016

Most existing studies on the wide-area differential global positioning system (WADGPS) employed a grid ionosphere model for error correction in the ionospheric delay. The present study discusses the application of satellite-based ionospheric delay model that provides an error model as a plane function with regard to individual satellites in order to improve accuracy in the WADGPS. The satellite-based ionospheric delay model was developed by Stanford University in the USA. In the present study, the algorithm in the model is applied to the WADGPS system and experimental results using measurements in the Korean Peninsula are presented. Around 1 m horizontal accuracy was exhibited in the existing planar fit grid model but when the satellite-based model was applied, correction performance within 1 m was verified.

• Proceedings of the KOR-KST Conference
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• 1998.10b
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• pp.298-298
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• 1998

The delay on two-lane, Two-way roads is a very important factor which tends to cause relatively high driver loads and too much delay often leads to traffic accidents. In this study a generalized form of delay estimation model was developed based on constant slow moving vehicle speeds, 100% no-passing zone, and flat terrain highway sections. To validate the model, a comparison was made with John Morrall's SMV(Slow Moving Vehicle)model as well as with TWOPAS model. Also a sensitivity analysis was performed to check accuracy of the model. It was found that the model was easy to apply and yet provided reasonable results for experimental conditions specified in the study. It was recommended that speed calculation procedure of the model be improved by further studies, so that the effect of speed acceleration or deceleration according to highway geometries on delay could be analyzed more accurately.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.723-726
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• 1998

Fault dropping is a very important part of test generation process. It is used to reduce test generation time. Test generation systems use fault simulation for the purpose of fault dropping by identifying detectable faults with generated test patterns. Two kinds of delay fault model is used in practice, path delay fault model and gate delay fault model. In this paper we propose an efficient method for gate delay test generation which shares second test vector.