• Title/Summary/Keyword: Delay Margin

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Analysis of Gate-Oxide Breakdown in CMOS Combinational Logics

  • Kim, Kyung Ki
    • Journal of Sensor Science and Technology
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    • v.28 no.1
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    • pp.17-22
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    • 2019
  • As CMOS technology scales down, reliability is becoming an important concern for VLSI designers. This paper analyzes gate-oxide breakdowns (i.e., the time-dependent dielectric-breakdown (TDDB) aging effect) as a reliability issue for combinational circuits with 45-nm technology. This paper shows simulation results for the noise margin, delay, and power using a single inverter-chain circuit, as well as the International Symposium on Circuits and Systems (ISCAS)'85 benchmark circuits. The delay and power variations in the presence of TDDB are also discussed in the paper. Finally, we propose a novel method to compensate for the logic failure due to dielectric breakdowns: We used a higher supply voltage and a negative ground voltage for the circuit. The proposed method was verified using the ISCAS'85 benchmark circuits.

The Design of PI Controller Using Saturation Function (포화 함수를 이용한 PI 제어기 설계)

  • Oh, Seung-Rohk
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.45 no.6
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    • pp.102-107
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    • 2008
  • We propose an autotuning algorithm for PI controller with unknown plant. The proposed algorithm uses a saturation function and time delay element as a test signal. Since the integral element of PI controller reduces a phase margin in the closed loop system, the closed loop system could be resulted in unstable with PI controller. To avoid unstable in the closed loop system with PI controller, the proposed algorithm identifies one point information in the 3rd quadrant of Nyquist plot with a time delay element. The proposed method improves an accuracy of one point identified information with one saturation function. We demonstrate a performance of the proposed method via a simulation.

A Study on the Discharge Characteristics of an Ac PDP with the Variation of Scan Electrode Driver (PDP 스캔 전극 구동방식에 따른 방전 특성의 변화에 관한 연구)

  • Kim, Joong-Kyun
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.19 no.8
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    • pp.13-18
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    • 2005
  • The variation of discharge characteristics of an ac PDP was observed with the charge of scan electrode driving circuit. Conventional scan electrode driving circuit provides two switches per one scan line, and the suggested one can be constituted by one switch per one scan line with the consideration of capacitive load characteristic of an ac PDP. To verify the workability of the suggested scheme, the performances of the ac PDP was investigated. The dynamic voltage margin was slightly decreased with the adoption of the suggested scheme, which is estimated to result from the misfiring of unselected discharge cells due to the deformation of voltage level of the neighboring scan electrode. In the observation of the delay characteristics of addressing discharge, the performances of the conventional circuit and the suggested one are assumed to be equivalent.

Design and Implementation of In-band Interference Reduction Module (동일대역 간섭저감기의 설계 및 구현)

  • Kang, Sanggee;Hong, Heonjin;Chong, Youngjun
    • Journal of IKEEE
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    • v.24 no.4
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    • pp.1028-1033
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    • 2020
  • The existing in-band interference reduction method recommends the physical separation distance between wireless devices and interference signals, and the interference can be suppressed through the separation distance. If the in-band interference signals can be reduced in a wireless device, a margin can be given to the physical separation distance. Since there is an effect of extending the receiver dynamic range of receivers, it is highly useful for interference reduction and improvement method. In this paper, the structure of an in-band analog IRM(Interference Reduction Module) is proposed and the design and implementation of the proposed analog IRM are described. To design an analog IRM, the interference reduction performance according to the delay mismatch, phase error and the number of delay lines that affect the performance of the analog IRM was simulated. The proposed analog IRM composed of 16 delay lines was implemented and the implemented IRM has the interference reduction performance of about 10dB for a 5G(NR-FR1-TM-1.1) signal having a 40MHz bandwidth at a center frequency of 3.32GHz. The analog IRM proposed in this paper can be used as an in-band interference canceller.

Application of an Adaptive Autopilot Design and Stability Analysis to an Anti-Ship Missile

  • Han, Kwang-Ho;Sung, Jae-Min;Kim, Byoung-Soo
    • International Journal of Aeronautical and Space Sciences
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    • v.12 no.1
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    • pp.78-83
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    • 2011
  • Traditional autopilot design requires an accurate aerodynamic model and relies on a gain schedule to account for system nonlinearities. This paper presents the control architecture applied to a dynamic model inversion at a single flight condition with an on-line neural network (NN) in order to regulate errors caused by approximate inversion. This eliminates the need for an extensive design process and accurate aerodynamic data. The simulation results using a developed full nonlinear 6 degree of freedom model are presented. This paper also presents the stability evaluation for control systems to which NNs were applied. Although feedback can accommodate uncertainty to meet system performance specifications, uncertainty can also affect the stability of the control system. The importance of robustness has long been recognized and stability margins were developed to quantify it. However, the traditional stability margin techniques based on linear control theory can not be applied to control systems upon which a representative non-linear control method, such as NNs, has been applied. This paper presents an alternative stability margin technique for NNs applied to control systems based on the system responses to an inserted gain multiplier or time delay element.

Design of Low Update Rate Phase Locked Loops with Application to Carrier Tracking in OFDM Systems

  • Raphaeli Dan;Yaniv Oded
    • Journal of Communications and Networks
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    • v.7 no.3
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    • pp.248-257
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    • 2005
  • In this paper, we develop design procedures for carrier tracking loop for orthogonal frequency division multiplexing (OFDM) systems or other systems of blocked data. In such communication systems, phase error measurements are made infrequent enough to invalidate the traditional loop design methodology which is based on analog loop design. We analyze the degradation in the OFDM schemes caused by the tracking loop and show how the performance is dependent on the rms phase error, where we distinguished between the effect of the variance in the average phase over the symbol and the effect of the phase change over the symbol. We derive the optimal tracking loop including optional delay in the loop caused by processing time. Our solution is general and includes arbitrary phase noise apd additive noise spectrums. In order to guarantee a well behaved solution, we have to check the design against margin constraints subject to uncertainties. In case the optimal loop does not meet the required margin constraints subjected to uncertainties, it is shown how to apply a method taken from control theory to find a controller. Alternatively, if we restrict the solution to first or second order loops, we give a simple loop design procedure which may be sufficient in many cases. Extensions of the method are shown for using both pilot symbols and data symbols in the OFDM receiver for phase tracking. We compare our results to other methods commonly used in OFDM receivers and we show that a large improvement can be gained.

A Study on Multi Level Load Shedding Control Scheme Strategy for Stabilization of the Korean Power System (국내 전력계통 안정화를 위한 다단계 부하차단 제어전략 수립에 관한 연구)

  • Lee, Yun-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.65 no.4
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    • pp.255-261
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    • 2016
  • Korean Power System are operating a load shedding system to prevent voltage instability phenomenon caused by severe line contingencies. In order to apply the load shedding scheme should be selected a location, amount, delay time. Current load shedding system is load shedding amount that has been calculated in the steady-state analysis to load shed the total amount in first level, load shedding amount calculated in advance, it is possible to perform an unnecessary load shedding. In this paper, set a multi-level load shedding control strategy step-by-step selection of load shedding amount for the prevention of excessive load shedding. In addition, through a voltage resilience analysis of the power system by applying motor load ratio and sensitivity parameter to selection the multi level load shedding ratio and delay time. For this reason, to take advantage of the limit data of interchange power, by utilizing interface power flow data to set a multi-level load shedding control strategy for the stabilization of the Korean Power System.

Simplified Controller Design Method for Digitally Controlled LCL-Type PWM Converter with Multi-resonant Quasi-PR Controller and Capacitor-Current-Feedback Active Damping

  • Lyu, Yongcan;Lin, Hua
    • Journal of Power Electronics
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    • v.14 no.6
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    • pp.1322-1333
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    • 2014
  • To track the sinusoidal current under stationary frame and suppress the effects of low-order grid harmonics, the multi-resonant quasi-proportional plus resonant (PR) controller has been extensively used for digitally controlled LCL-type pulse-width modulation (PWM) converters with capacitor-current-feedback active damping. However, designing the controller is difficult because of its high order and large number of parameters. Moreover, the computation and PWM delays of the digitally controlled system significantly affect damping performance. In this study, the delay effect is analyzed by using the Nyquist diagrams and the system stability constraint condition can be obtained based on the Nyquist stability criterion. Moreover, impact analysis of the control parameters on the current loop performance, that is, steady-state error and stability margin, identifies that different control parameters play different decisive roles in current loop performance. Based on the analysis, a simplified controller design method based on the system specifications is proposed. Following the method, two design examples are given, and the experimental results verify the practicability and feasibility of the proposed design method.

A Novel Air-Bridge Type Gate-Data Line Inter-Crossing to Reduce Signal Delay for Large Size AMLCD (대면적 AMLCD의 신호 지연 감소를 위해 Air-gap을 갖는 게이트-데이터 라인 교차 구조)

  • Park, Jin-Woo;Kang, Ji-Hoon;Lee, Min-Cheol;Han, Min-Koo
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.12
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    • pp.768-772
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    • 1999
  • A new TFT-LCD panel with air-bridge type gate to data line inter-crossing has been proposed and its characteristics have been measured. The proposed structure has air-gap between gate and data line inter-crossing. This air-bridge TFT-LCD panel has very small capacitance between gate and data line. The new panes structure achieves 9 times fast signal propagation compared with conventional panel, which enables to have enough design margin for 20-inch diagonal and larger size UXGA panel. We have examined thermal and mechanical durability of new panel to verify applicability for commercial AMLCD production. After TEOS and polyimide passivation, this panel withstood a thermal stress at $250^{\circ}C$ and a mechanical stress during the rubbing process.

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A Study on the Method of Gain Setting of Digital Governor by Dynamic Calculation for Marine Prime Movers (선박 주기관 디지털 거버너의 동적 게인 설정법에 관한 연구)

  • 강인철;최순만;최재성
    • Proceedings of the Korean Society of Marine Engineers Conference
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    • 2002.05a
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    • pp.251-259
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    • 2002
  • The design concept of diesel engines for sea-going ships has been directed to Low-speed/Long-Stroke type to improve the efficiencies of combustion and propelling. But the time-delay property inevitable at such low speed engines gives much difficulties for governors to control the engine speed because they would be apt to go into unstable region especially when operating at low speed. The purpose of this paper is to study the problem of how the governor gain can be calculated dynamically in accordance with the variance of engine speed at least for an engine to be stable. In this study, the property of diesel engine was described as composed of combustion element including dead time and rotating element, and the ultimate gain for the speed control system to be located on the condition of stability limit was proposed based on the frequency characteristics. And the target gains with optimized stability also were proposed by giving proper margin to these ultimate conditions. The results were applied to a model system and the availability was confirmed to be satisfactory.

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