• The Journal of the Acoustical Society of Korea
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• v.22 no.4E
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• pp.167-175
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• 2003

Shear wave velocity was measured and grain size analysis was conducted on two core samples obtained in unconsolidated marine sediments of the western continental margin, the East Sea. A pulse transmission technique based on the Hamilton frame was used to measure shear wave velocity. Duomorph ceramic bender transducer-receiver elements were used to generate and detect shear waves in sediment samples. Time delay was calculated by changing the sample length from the transducer-receiver element. Time delay is 43.18 μs and shear wave velocity (22.49 m/s) is calculated from the slope of regression line. Shear wave velocities of station 1 and 2 range from 8.9 to 19.0 m/s and from 8.8 to 22 mis, respectively. Shear wave velocities with depth in both cores are qualitatively in agreement with the compared model〔1〕, although the absolute value is different. The sediment type of two core samples is mud (mean grain size, 8-9Φ). Shear wave velocity generally increases with sediment depth, which is suggesting normally consolidated sediments. The complicated variation of velocity anisotropy with depth at station 2 is probably responsible for sediment disturbance by possible gas effect.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2589-2592
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• 2003

In this paper, a robust mixed H$_2$/H$\_$$\infty$/ output feedback control method is applied to the design of loop filter for PLL carrier phase tracking. The proposed method successfully copes with large S-curve slope uncertainty and a significant decision delay in the closed-loop that may exist In modern receivers due to a convolutional decoder or an equalizer. The objective is to design an output feedback controller which minimizes the H$_2$performance while satisfying the H$\_$$\infty$/ performance to guarantee the gain margin and phase margin for linear time invariant(LTI) polytopic uncertain systems. LMIs based approach is given to solve this problem. We can verify the H$\_$$\infty$/ performance satisfaction and minimize the phase detector error through the simulation result.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.506-507
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• 2005

The effects of addition of $D_2$ to conventional gases [Ne-Xe and He-Ne-Xe] on the discharge characteristics were investigated in this work with the aim of improving the voltage margin, the wall charge and the jitter. The addition of an extremely small gas-inlet amounts of $D_2$ increased the number of electrons which improves. the $Xe^*$ density and $Xe_2^*$ density. As a result, the voltage margin, the jitter and the wall charge increased.

• Journal of Energy Engineering
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• v.24 no.2
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• pp.40-44
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• 2015

Sensitivity on the reactor safety was evaluated for the safety margin and time delay applied to the opening pressure of liquid relief valve(LRV) of the primary heat transport system(PHTS) in the pressurized heavy water reactor(PHWR) type nuclear power plant. Since the LRV is the pressure boundary for the PHTS in the safety analysis, the operating of LRV has a significant effect on the safety analysis results. Therefore it is required during the regulatory review of Wolsong Unit 1 safety analysis to find the safety effect of the application of safety margin and time delay to the LRV opening pressure for the safety analysis of PHTS pressurizing events.

• Progress in Superconductivity and Cryogenics
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• v.8 no.2
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• pp.17-19
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• 2006

A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

• Smart Structures and Systems
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• v.25 no.6
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• pp.719-732
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• 2020

Real-time hybrid simulation (RTHS) which combines physical experiment with numerical simulation is an advanced method to investigate dynamic responses of structures subjected to earthquake excitation. The desired displacement computed from the numerical substructure is applied to the experimental substructure by a servo-hydraulic actuator in real time. However, the magnitude decay and phase delay resulted from the dynamics of the servo-hydraulic system affect the accuracy and stability of a RTHS. In this study, a robust stability analysis procedure for a general single-degree-of-freedom structure is proposed which considers the uncertainty of servo-hydraulic system dynamics. For discussion purposes, the experimental substructure is a portion of the entire structure in terms of a ratio of stiffness, mass, and damping, respectively. The dynamics of the servo-hydraulic system is represented by a multiplicative uncertainty model which is based on a nominal system and a weight function. The nominal system can be obtained by conducting system identification prior to the RTHS. A first-order weight function formulation is proposed which needs to cover the worst possible uncertainty envelope over the frequency range of interest. Then, the Nyquist plot of the perturbed system is adopted to determine the robust stability margin of the RTHS. In addition, three common delay compensation methods are applied to the RTHS loop to investigate the effect of delay compensation on the robust stability. Numerical simulation and experimental validation results indicate that the proposed procedure is able to obtain a robust stability margin in terms of mass, damping, and stiffness ratio which provides a simple and conservative approach to assess the stability of a RTHS before it is conducted.

• Restorative Dentistry and Endodontics
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• v.25 no.2
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• pp.299-308
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• 2000

The purpose of this in vitro study was to evaluate the microleakage of 5 curing methods in class V composite restorations which are composed of two-step light curing, pulse-delay cure, low curing-light intensity, moderate curing-light intensity and high curing-light intensity. In this study, class V cavities were prepared on buccal and lingual surfaces of 50 extracted human upper or lower molars on cementum margin. Single Bond adhesive and Z-100 shade A2 were applied for each group following the manufacture's instruction. The experimental teeth were randomly divided into 5 groups of 10 samples (20 surfaces) each. Group 1: two-step light curing; Group 2: pulse-delay cure; Group 3: low curing-light intensity; Group 4: moderate curing-light intensity; Group 5: high curing-light intensity. After 500 thermocycling between $5^{\circ}C$ and $55^{\circ}C$, the 60 teeth were placed in 2% methylene blue dye for 24 hours, then rinsed with tab water. The specimens were embedded in clear resin, then sectioned buccolingually through the center of restoration with a low speed diamond saw. The dye penetration on each of the specimen was then observed with a stereomicroscope at ${\times}20$. The composite resin/tooth interfaces were examined under Scanning Electron Microscopy. The results were statistically analyzed using the Kruskal-Wallis One Way ANOVA and Dunn's Method. The results of this study were as follows. 1. In all groups, the leakage values seen at the enamel margin were significantly lower than those seen at the dentin margin(P<0.05). 2. No group in this study showed significant differences in leakage values at both the enamel and the dentin margins(P<0.05). 3. In all groups, the gaps seen at the enamel margin were significantly lower than those seen at the dentin margin(P<0.05). 4. The gaps in this study showed significant differences and two-step light-curing and low curing-light intensity produced significant less gap than high curing-light intensity(P<0.05).

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.932-934
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• 2006

A relationship between discharge delay time and the aging method were investigated: A-Y (Address electrode - Scan electrode) aging and conventional X-Y(Common electrode - Scan electrode) aging with the variation of sustain voltage beyond self-erasing discharge. Although A-Y aging decreases discharge delay time, it has several drawbacks like non-uniformity of discharge, degradation of luminous efficiency and a color temperature. In a conventional aging condition which is carried out near the mid-margin voltage, discharge delay time is short in low voltage and high frequency condition. As an alternative to conventional voltage aging, high voltage aging is suggested which is carried out at self-erasing sustain voltage region. High voltage aging shows lower discharge delay time and fast aging speed than conventional voltage aging.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.14-21
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• 2009

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a $0.18{\mu}m$ CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a $0.18{\mu}m$ CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.